Add RVV f16-f32-vcvt kernels and configs.

cmake/gen/rvvfp16arith_microkernels.cmake

@@ -12,6 +12,9 @@
 SET(PROD_RVVFP16ARITH_MICROKERNEL_SRCS)
 
 SET(NON_PROD_RVVFP16ARITH_MICROKERNEL_SRCS
+  src/f16-f32-vcvt/gen/f16-f32-vcvt-rvvfp16arith-u1v.c
+  src/f16-f32-vcvt/gen/f16-f32-vcvt-rvvfp16arith-u2v.c
+  src/f16-f32-vcvt/gen/f16-f32-vcvt-rvvfp16arith-u4v.c
   src/f16-vclamp/gen/f16-vclamp-rvvfp16arith-u1v.c
   src/f16-vclamp/gen/f16-vclamp-rvvfp16arith-u2v.c
   src/f16-vclamp/gen/f16-vclamp-rvvfp16arith-u4v.c

gen/rvvfp16arith_microkernels.bzl

@@ -9,6 +9,9 @@ PROD_RVVFP16ARITH_MICROKERNEL_SRCS = [
 ]
 
 NON_PROD_RVVFP16ARITH_MICROKERNEL_SRCS = [
+    "src/f16-f32-vcvt/gen/f16-f32-vcvt-rvvfp16arith-u1v.c",
+    "src/f16-f32-vcvt/gen/f16-f32-vcvt-rvvfp16arith-u2v.c",
+    "src/f16-f32-vcvt/gen/f16-f32-vcvt-rvvfp16arith-u4v.c",
     "src/f16-vclamp/gen/f16-vclamp-rvvfp16arith-u1v.c",
     "src/f16-vclamp/gen/f16-vclamp-rvvfp16arith-u2v.c",
     "src/f16-vclamp/gen/f16-vclamp-rvvfp16arith-u4v.c",

scripts/generate-f16-f32-vcvt.sh

@@ -18,6 +18,11 @@ tools/xngen src/f16-f32-vcvt/neon-int32.c.in -D BATCH_TILE=32 -o src/f16-f32-vcv
 tools/xngen src/f16-f32-vcvt/neonfp16.c.in -D BATCH_TILE=8  -o src/f16-f32-vcvt/gen/f16-f32-vcvt-neonfp16-u8.c &
 tools/xngen src/f16-f32-vcvt/neonfp16.c.in -D BATCH_TILE=16 -o src/f16-f32-vcvt/gen/f16-f32-vcvt-neonfp16-u16.c &
 
+################################ RISC-V Vector ################################
+tools/xngen src/f16-f32-vcvt/rvvfp16arith.c.in -D LMUL=1 -o src/f16-f32-vcvt/gen/f16-f32-vcvt-rvvfp16arith-u1v.c &
+tools/xngen src/f16-f32-vcvt/rvvfp16arith.c.in -D LMUL=2 -o src/f16-f32-vcvt/gen/f16-f32-vcvt-rvvfp16arith-u2v.c &
+tools/xngen src/f16-f32-vcvt/rvvfp16arith.c.in -D LMUL=4 -o src/f16-f32-vcvt/gen/f16-f32-vcvt-rvvfp16arith-u4v.c &
+
 ################################# x86 128-bit #################################
 tools/xngen src/f16-f32-vcvt/sse-int16.c.in -D SSE=2 -D AVX=0 -D BATCH_TILE=8  -o src/f16-f32-vcvt/gen/f16-f32-vcvt-sse2-int16-u8.c &
 tools/xngen src/f16-f32-vcvt/sse-int16.c.in -D SSE=2 -D AVX=0 -D BATCH_TILE=16 -o src/f16-f32-vcvt/gen/f16-f32-vcvt-sse2-int16-u16.c &

src/f16-f32-vcvt/f16-f32-vcvt.h

@@ -85,6 +85,12 @@ XNN_CVT_UKERNEL_WITH_PARAMS(0, xnn_f16_f32_vcvt_ukernel__wasmrelaxedsimd_int32_u
 XNN_CVT_UKERNEL_WITH_PARAMS(0, xnn_f16_f32_vcvt_ukernel__wasmrelaxedsimd_int32_u32, 32, false, xnn_float16, float, void, NULL)
 #endif  // XNN_ARCH_WASMRELAXEDSIMD
 
+#if XNN_ARCH_RISCV && XNN_ENABLE_RISCV_FP16_VECTOR
+XNN_CVT_UKERNEL_WITH_PARAMS(xnn_arch_riscv_vector_fp16_arith, xnn_f16_f32_vcvt_ukernel__rvvfp16arith_u1v, 1, true, xnn_float16, float, void, NULL)
+XNN_CVT_UKERNEL_WITH_PARAMS(xnn_arch_riscv_vector_fp16_arith, xnn_f16_f32_vcvt_ukernel__rvvfp16arith_u2v, 2, true, xnn_float16, float, void, NULL)
+XNN_CVT_UKERNEL_WITH_PARAMS(xnn_arch_riscv_vector_fp16_arith, xnn_f16_f32_vcvt_ukernel__rvvfp16arith_u4v, 4, true, xnn_float16, float, void, NULL)
+#endif
+
 XNN_CVT_UKERNEL_WITH_PARAMS(0, xnn_f16_f32_vcvt_ukernel__scalar_u1, 1, false, xnn_float16, float, void, NULL)
 XNN_CVT_UKERNEL_WITH_PARAMS(0, xnn_f16_f32_vcvt_ukernel__scalar_u2, 2, false, xnn_float16, float, void, NULL)
 XNN_CVT_UKERNEL_WITH_PARAMS(0, xnn_f16_f32_vcvt_ukernel__scalar_u3, 3, false, xnn_float16, float, void, NULL)

src/f16-f32-vcvt/gen/f16-f32-vcvt-rvvfp16arith-u1v.c

@@ -0,0 +1,40 @@
+// Auto-generated file. Do not edit!
+//   Template: src/f16-f32-vcvt/rvvfp16arith.c.in
+//   Generator: tools/xngen
+//
+// Copyright (c) 2025 Institute of Software Chinese Academy of Sciences (ISCAS).
+//
+// This source code is licensed under the BSD-style license found in the
+// LICENSE file in the root directory of this source tree.
+
+#include <assert.h>
+
+#include <riscv_vector.h>
+
+#include "xnnpack/vcvt.h"
+
+
+void xnn_f16_f32_vcvt_ukernel__rvvfp16arith_u1v(
+   size_t batch,
+   const xnn_float16* input,
+   float* output,
+   const void* params)
+{
+  assert(batch != 0);
+  assert(batch % sizeof(xnn_float16) == 0);
+  assert(input != NULL);
+  assert(output != NULL);
+
+  batch >>= XNN_LOG2_SIZEOF_HALF;
+
+  const _Float16* i = (const _Float16*) input;
+  for (; batch > 0;) {
+    const int32_t n = __riscv_vsetvl_e16m1(batch); batch -= n;
+
+    vfloat16m1_t x_f16v = __riscv_vle16_v_f16m1(i, n); i += n;
+
+    vfloat32m2_t y_f32v = __riscv_vfwcvt_f_f_v_f32m2(x_f16v, n);
+
+    __riscv_vse32_v_f32m2(output, y_f32v, n); output += n;
+  }
+}

src/f16-f32-vcvt/gen/f16-f32-vcvt-rvvfp16arith-u2v.c

@@ -0,0 +1,40 @@
+// Auto-generated file. Do not edit!
+//   Template: src/f16-f32-vcvt/rvvfp16arith.c.in
+//   Generator: tools/xngen
+//
+// Copyright (c) 2025 Institute of Software Chinese Academy of Sciences (ISCAS).
+//
+// This source code is licensed under the BSD-style license found in the
+// LICENSE file in the root directory of this source tree.
+
+#include <assert.h>
+
+#include <riscv_vector.h>
+
+#include "xnnpack/vcvt.h"
+
+
+void xnn_f16_f32_vcvt_ukernel__rvvfp16arith_u2v(
+   size_t batch,
+   const xnn_float16* input,
+   float* output,
+   const void* params)
+{
+  assert(batch != 0);
+  assert(batch % sizeof(xnn_float16) == 0);
+  assert(input != NULL);
+  assert(output != NULL);
+
+  batch >>= XNN_LOG2_SIZEOF_HALF;
+
+  const _Float16* i = (const _Float16*) input;
+  for (; batch > 0;) {
+    const int32_t n = __riscv_vsetvl_e16m2(batch); batch -= n;
+
+    vfloat16m2_t x_f16v = __riscv_vle16_v_f16m2(i, n); i += n;
+
+    vfloat32m4_t y_f32v = __riscv_vfwcvt_f_f_v_f32m4(x_f16v, n);
+
+    __riscv_vse32_v_f32m4(output, y_f32v, n); output += n;
+  }
+}

src/f16-f32-vcvt/gen/f16-f32-vcvt-rvvfp16arith-u4v.c

@@ -0,0 +1,40 @@
+// Auto-generated file. Do not edit!
+//   Template: src/f16-f32-vcvt/rvvfp16arith.c.in
+//   Generator: tools/xngen
+//
+// Copyright (c) 2025 Institute of Software Chinese Academy of Sciences (ISCAS).
+//
+// This source code is licensed under the BSD-style license found in the
+// LICENSE file in the root directory of this source tree.
+
+#include <assert.h>
+
+#include <riscv_vector.h>
+
+#include "xnnpack/vcvt.h"
+
+
+void xnn_f16_f32_vcvt_ukernel__rvvfp16arith_u4v(
+   size_t batch,
+   const xnn_float16* input,
+   float* output,
+   const void* params)
+{
+  assert(batch != 0);
+  assert(batch % sizeof(xnn_float16) == 0);
+  assert(input != NULL);
+  assert(output != NULL);
+
+  batch >>= XNN_LOG2_SIZEOF_HALF;
+
+  const _Float16* i = (const _Float16*) input;
+  for (; batch > 0;) {
+    const int32_t n = __riscv_vsetvl_e16m4(batch); batch -= n;
+
+    vfloat16m4_t x_f16v = __riscv_vle16_v_f16m4(i, n); i += n;
+
+    vfloat32m8_t y_f32v = __riscv_vfwcvt_f_f_v_f32m8(x_f16v, n);
+
+    __riscv_vse32_v_f32m8(output, y_f32v, n); output += n;
+  }
+}

src/f16-f32-vcvt/rvvfp16arith.c.in

@@ -0,0 +1,38 @@
+// Copyright (c) 2025 Institute of Software Chinese Academy of Sciences (ISCAS).
+//
+// This source code is licensed under the BSD-style license found in the
+// LICENSE file in the root directory of this source tree.
+
+$assert LMUL in [1, 2, 4]
+$LMUL_32 = {1: "2", 2: "4", 4: "8"}[LMUL]
+#include <assert.h>
+
+#include <riscv_vector.h>
+
+#include "xnnpack/vcvt.h"
+
+
+void xnn_f16_f32_vcvt_ukernel__rvvfp16arith_u${LMUL}v(
+   size_t batch,
+   const xnn_float16* input,
+   float* output,
+   const void* params)
+{
+  assert(batch != 0);
+  assert(batch % sizeof(xnn_float16) == 0);
+  assert(input != NULL);
+  assert(output != NULL);
+
+  batch >>= XNN_LOG2_SIZEOF_HALF;
+
+  const _Float16* i = (const _Float16*) input;
+  for (; batch > 0;) {
+    const int32_t n = __riscv_vsetvl_e16m${LMUL}(batch); batch -= n;
+
+    vfloat16m${LMUL}_t x_f16v = __riscv_vle16_v_f16m${LMUL}(i, n); i += n;
+
+    vfloat32m${LMUL_32}_t y_f32v = __riscv_vfwcvt_f_f_v_f32m${LMUL_32}(x_f16v, n);
+
+    __riscv_vse32_v_f32m${LMUL_32}(output, y_f32v, n); output += n;
+  }
+}