This CL introduces several enhancements to the dot product scheduling and parallelism logic:

[copybara-service]

This CL introduces several enhancements to the dot product scheduling and parallelism logic:

Cache-Aware Scheduling:
The schedule_dot function now utilizes cpu_info (including L1, L2, and L3 cache sizes and L3 sharing) to make more informed tiling decisions. Additions:

• A fast path for small matrices that fit entirely within the L2 cache, skipping K-tiling.
• Outer k-loop tiling sized to fit within the L2 cache. The smaller of matrix A or B is kept cache-resident.
• If both A and B are contiguous, we make use of L3 and effective prefetching to hide load latency.

Dynamic Tiling for Parallelism:
choose_split_factors now dynamically determines the 2D tiling (m_split, n_split) for parallel execution. Additions:

• Inclusion of element sizes (elem_a, elem_b, elem_c) for more accurate footprint calculations.
• A fast path for very small workloads to run on a single thread.
• Asymmetric matrix shape handling (M-heavy or N-heavy) through aspect ratios, and increase in target footprints to prevent inefficient slivers.