Adds device, ioctls, and new CapProfiling capability

pkg/abi/nvgpu/classes.go

@@ -77,6 +77,7 @@ const (
 	GF100_ZBC_CLEAR                  = 0x00009096
 	GF100_SUBDEVICE_INFOROM          = 0x000090e7
 	GF100_PROFILER                   = 0x000090cc
+	MAXWELL_PROFILER_DEVICE          = 0x0000b2cc
 	GF100_SUBDEVICE_MASTER           = 0x000090e6
 	FERMI_VASPACE_A                  = 0x000090f1
 	KEPLER_CHANNEL_GROUP_A           = 0x0000a06c
@@ -761,3 +762,13 @@ type NV_OFA_ALLOCATION_PARAMETERS_V545 struct {
 	NV_OFA_ALLOCATION_PARAMETERS
 	EngineInstance uint32
 }
+
+// NVB2CC_ALLOC_PARAMETERS is the alloc params type for MAXWELL_PROFILER_DEVICE,
+// from src/common/sdk/nvidia/inc/class/clb2cc.h.
+//
+// +marshal
+type NVB2CC_ALLOC_PARAMETERS struct {
+	_              structs.HostLayout
+	HClientTarget  Handle
+	HContextTarget Handle
+}

pkg/abi/nvgpu/ctrl.go

@@ -579,7 +579,9 @@ const (
 	NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_V575  = NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT - 1
 	NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS_V575           = NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS - 1
 	NV2080_CTRL_CMD_FB_GET_OFFLINED_PAGES                          = 0x20801322
+	NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE                             = 0x2080130e
 	NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION = 0x20801355
+	NV2080_CTRL_CMD_FB_GET_FS_INFO                                 = 0x20801346
 )
 
 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h:
@@ -639,13 +641,15 @@ const (
 	NV2080_CTRL_CMD_GPU_GET_SKYLINE_INFO                 = 0x2080019f
 	NV2080_CTRL_CMD_GPU_GET_CHIP_DETAILS                 = 0x208001a4
 	NV2080_CTRL_CMD_GPU_GET_RECOVERY_ACTION              = 0x208001b2
+	NV2080_CTRL_CMD_GPU_EXEC_REG_OPS                     = 0x20800122
 )
 
 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h:
 const (
 	NV2080_CTRL_CMD_GR_GET_INFO                   = 0x20801201
 	NV2080_CTRL_CMD_GR_GET_ZCULL_INFO             = 0x20801206
 	NV2080_CTRL_CMD_GR_CTXSW_ZCULL_BIND           = 0x20801208
+	NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS = 0x2080120f
 	NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE  = 0x20801210
 	NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_SIZE        = 0x20801218
 	NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER        = 0x2080121b
@@ -687,6 +691,44 @@ func (p *NV2080_CTRL_GR_GET_INFO_PARAMS) CtrlInfoList() P64 {
 	return p.InfoList
 }
 
+// NV2080_CTRL_GPU_REG_OP is the type of an individual register operation,
+// from src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h.
+//
+// +marshal
+type NV2080_CTRL_GPU_REG_OP struct {
+	_               structs.HostLayout
+	RegOp           uint8
+	RegType         uint8
+	RegStatus       uint8
+	RegQuad         uint8
+	RegGroupMask    uint32
+	RegSubGroupMask uint32
+	RegOffset       uint32
+	RegValueHi      uint32
+	RegValueLo      uint32
+	RegAndNMaskHi   uint32
+	RegAndNMaskLo   uint32
+}
+
+// CtrlGpuRegOpSize is sizeof(NV2080_CTRL_GPU_REG_OP).
+var CtrlGpuRegOpSize = uint32((*NV2080_CTRL_GPU_REG_OP)(nil).SizeBytes())
+
+// NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS is the params type for
+// NV2080_CTRL_CMD_GPU_EXEC_REG_OPS, from
+// src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h.
+//
+// +marshal
+type NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS struct {
+	_                 structs.HostLayout
+	HClientTarget     Handle
+	HChannelTarget    Handle
+	BNonTransactional uint32
+	Reserved00        [2]uint32
+	RegOpCount        uint32
+	RegOps            P64
+	GRRouteInfo       NV0080_CTRL_GR_ROUTE_INFO
+}
+
 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h:
 const (
 	NV2080_CTRL_CMD_MC_GET_ARCH_INFO      = 0x20801701
@@ -786,6 +828,7 @@ const (
 const (
 	NVA06C_CTRL_CMD_GPFIFO_SCHEDULE = 0xa06c0101
 	NVA06C_CTRL_CMD_SET_TIMESLICE   = 0xa06c0103
+	NVA06C_CTRL_CMD_GET_TIMESLICE   = 0xa06c0104
 	NVA06C_CTRL_CMD_PREEMPT         = 0xa06c0105
 )
 
@@ -795,6 +838,33 @@ const (
 	NVA06F_CTRL_CMD_BIND            = 0xa06f0104
 )
 
+// From src/common/sdk/nvidia/inc/ctrl/ctrl90cc.h:
+const (
+	NV90CC_CTRL_CMD_POWER_REQUEST_FEATURES = 0x90cc0301
+	NV90CC_CTRL_CMD_POWER_RELEASE_FEATURES = 0x90cc0302
+)
+
+// From src/common/sdk/nvidia/inc/ctrl/ctrlb0cc.h:
+const (
+	NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY        = 0xb0cc0101
+	NVB0CC_CTRL_CMD_RELEASE_HWPM_LEGACY        = 0xb0cc0102
+	NVB0CC_CTRL_CMD_RESERVE_PM_AREA_SMPC       = 0xb0cc0103
+	NVB0CC_CTRL_CMD_RELEASE_PM_AREA_SMPC       = 0xb0cc0104
+	NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM           = 0xb0cc0105
+	NVB0CC_CTRL_CMD_FREE_PMA_STREAM            = 0xb0cc0106
+	NVB0CC_CTRL_CMD_BIND_PM_RESOURCES          = 0xb0cc0107
+	NVB0CC_CTRL_CMD_UNBIND_PM_RESOURCES        = 0xb0cc0108
+	NVB0CC_CTRL_CMD_PMA_STREAM_UPDATE_GET_PUT  = 0xb0cc0109
+	NVB0CC_CTRL_CMD_EXEC_REG_OPS               = 0xb0cc010a
+	NVB0CC_CTRL_CMD_RESERVE_PM_AREA_PC_SAMPLER = 0xb0cc010b
+	NVB0CC_CTRL_CMD_RELEASE_PM_AREA_PC_SAMPLER = 0xb0cc010c
+	NVB0CC_CTRL_CMD_GET_TOTAL_HS_CREDITS       = 0xb0cc010d
+	NVB0CC_CTRL_CMD_SET_HS_CREDITS             = 0xb0cc010e
+	NVB0CC_CTRL_CMD_RESERVE_CCU_PROF           = 0xb0cc0119
+	NVB0CC_CTRL_CMD_POWER_REQUEST_FEATURES     = 0xb0cc0301
+	NVB0CC_CTRL_CMD_POWER_RELEASE_FEATURES     = 0xb0cc0302
+)
+
 // From src/common/sdk/nvidia/inc/ctrl/ctrlcb33.h:
 const (
 	NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES     = 0xcb330101

pkg/sentry/devices/nvproxy/frontend_unsafe.go

@@ -143,6 +143,41 @@ func ctrlGetNvU32ListInvoke(fi *frontendIoctlState, ioctlParams *nvgpu.NVOS54_PA
 	return n, nil
 }
 
+func ctrlGpuExecRegOps(fi *frontendIoctlState, ioctlParams *nvgpu.NVOS54_PARAMETERS) (uintptr, error) {
+	var ctrlParams nvgpu.NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS
+	if ctrlParams.SizeBytes() != int(ioctlParams.ParamsSize) {
+		return 0, linuxerr.EINVAL
+	}
+	if _, err := ctrlParams.CopyIn(fi.t, addrFromP64(ioctlParams.Params)); err != nil {
+		return 0, err
+	}
+	if ctrlParams.RegOps == 0 {
+		return rmControlSimple(fi, ioctlParams)
+	}
+	if !rmapiParamsSizeCheck(ctrlParams.RegOpCount, nvgpu.CtrlGpuRegOpSize) {
+		return 0, frontendFailWithStatus(fi, ioctlParams, nvgpu.NV_ERR_INVALID_ARGUMENT)
+	}
+	regOps := make([]byte, uint64(ctrlParams.RegOpCount)*uint64(nvgpu.CtrlGpuRegOpSize))
+	if _, err := fi.t.CopyInBytes(addrFromP64(ctrlParams.RegOps), regOps); err != nil {
+		return 0, err
+	}
+
+	origRegOps := ctrlParams.RegOps
+	ctrlParams.RegOps = p64FromPtr(unsafe.Pointer(&regOps[0]))
+	n, err := rmControlInvoke(fi, ioctlParams, &ctrlParams)
+	ctrlParams.RegOps = origRegOps
+	if err != nil {
+		return n, err
+	}
+	if _, err := fi.t.CopyOutBytes(addrFromP64(ctrlParams.RegOps), regOps); err != nil {
+		return n, err
+	}
+	if _, err := ctrlParams.CopyOut(fi.t, addrFromP64(ioctlParams.Params)); err != nil {
+		return n, err
+	}
+	return n, nil
+}
+
 func ctrlDevGRGetCapsInvoke(fi *frontendIoctlState, ioctlParams *nvgpu.NVOS54_PARAMETERS, ctrlParams *nvgpu.NV0080_CTRL_GET_CAPS_PARAMS, capsTbl []byte) (uintptr, error) {
 	origCapsTbl := ctrlParams.CapsTbl
 	ctrlParams.CapsTbl = p64FromPtr(unsafe.Pointer(&capsTbl[0]))

pkg/sentry/devices/nvproxy/nvconf/caps.go

@@ -22,7 +22,7 @@ import (
 )
 
 // DriverCaps is a set of NVIDIA driver capabilities as a bitmask.
-type DriverCaps uint8
+type DriverCaps uint16
 
 // Individual NVIDIA driver capabilities.
 const (
@@ -36,8 +36,11 @@ const (
 	CapCompat32
 
 	// These correspond loosely to capabilities defined in
-	// src/nvidia/inc/kernel/os/capability.h.
+	// src/nvidia/inc/kernel/os/capability.h. These are not
+	// covered by "all" and are considered privileged capabilities,
+	// requiring to be enabled explicitly.
 	CapFabricIMEXManagement // NV_RM_CAP_SYS_FABRIC_IMEX_MGMT
+	CapProfiling            // GPU hardware performance counter access (Nsight Compute/Systems)
 
 	numValidCaps int = iota
 )
@@ -52,7 +55,7 @@ const (
 
 	// SupportedDriverCaps is the set of driver capabilities that are supported by
 	// nvproxy.
-	SupportedDriverCaps = AllContainerDriverCaps | CapFabricIMEXManagement
+	SupportedDriverCaps = AllContainerDriverCaps | CapFabricIMEXManagement | CapProfiling
 
 	// AllContainerDriverCaps is the subset of SupportedDriverCaps that are
 	// enabled when enabling "all" capabilities is requested, which excludes
@@ -86,8 +89,10 @@ func (c DriverCaps) individualString() string {
 		return "compat32"
 	case CapFabricIMEXManagement:
 		return "fabric-imex-mgmt"
+	case CapProfiling:
+		return "profiling"
 	default:
-		panic(fmt.Sprintf("capability has no string mapping: %x", uint8(c)))
+		panic(fmt.Sprintf("capability has no string mapping: %x", uint16(c)))
 	}
 }
 
@@ -99,7 +104,7 @@ func (c DriverCaps) individualNVIDIAFlag() string {
 	case CapCompute, CapDisplay, CapGraphics, CapNGX, CapUtility, CapVideo, CapCompat32:
 		return fmt.Sprintf("--%s", c.individualString())
 	default:
-		panic(fmt.Sprintf("capability has no NVIDIA flag mapping: %x", uint8(c)))
+		panic(fmt.Sprintf("capability has no NVIDIA flag mapping: %x", uint16(c)))
 	}
 }