Skip to content

Conversation

@ramosian-glider
Copy link
Member


Before sending a pull request, please review Contribution Guidelines:
https://github.com/google/syzkaller/blob/master/docs/contributing.md


Ensure L2 correctly exits to L1 on CPUID and resumes properly.
Add a test.
Enable basic RDTSC handling. Ensure that Intel hosts exit on RDTSC
in L2, and that both Intel and AMD can handle RDTSC exits.

Add amd64-syz_kvm_nested_vmresume-rdtsc to test that.
While at it, fix a bug in rdmsr() that apparently lost the top 32 bits.

Also fix a bug in Intel's Secondary Processor-based Controls:
we were incorrectly using the top 32 bits of
X86_MSR_IA32_VMX_PROCBASED_CTLS2 to enable all the available controls
without additional setup. This only worked because rdmsr() zeroed out
those top bits.
Enable basic RDTSCP handling. Ensure that Intel hosts exit on RDTSCP
in L2, and that both Intel and AMD can handle RDTSCP exits.

Add amd64-syz_kvm_nested_vmresume-rdtscp to test that.
@ramosian-glider
Copy link
Member Author

PTAL

@ramosian-glider ramosian-glider added this pull request to the merge queue Nov 21, 2025
Merged via the queue into google:master with commit 4d2a94c Nov 21, 2025
19 checks passed
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

2 participants