Add support for array-typed parameters to VAST. #3685
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These were representable but were unusable because they could not be converted to a IndexableExpression. Also add this capability to the C API.
meheff
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Jan 14, 2026
These were representable but were unusable because they could not be converted to a IndexableExpression. Also add this capability to the C API.
mikex-oss
reviewed
Jan 20, 2026
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| EXPECT_EQ(m->Emit(nullptr), | ||
| R"(module top; | ||
| parameter P0[2] = '{'0, '0}; |
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I don't believe it's valid SystemVerilog to have an unpacked param without an explicit data type. Similar below.
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Thanks for the review. Sorry I missed it earlier.
There is not a specific example of this construct in the spec, but the grammar production rules allow it (6.20.1) and it doesn't appear to be explicitly disallowed. There is some discussion about aggregate constants at the end of 6.20.2 where such an exception seemingly would be made. I assume it behaves just as an array of the implicit data type (32-bit signed logic in SV).
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Both Verific and VCS report syntax errors in this case. E.g.
Error-[SE] Syntax error
Following verilog source has syntax error :
...
token is '='
parameter P0[2] = '{'0, '0};
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These were representable but were unusable because they could not be converted to a IndexableExpression. Also add unpacked array parameters and array assignment to the C API.