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| 1 | +/* plic_test.c — NyanSoC PLIC hardware verification |
| 2 | + * |
| 3 | + * Tests: |
| 4 | + * 1. Reset state: all PLIC registers read as 0. |
| 5 | + * 2. Priority / enable / threshold registers are R/W. |
| 6 | + * 3. Send a UART TX byte, loop it back via RX → PLIC pending bit set. |
| 7 | + * 4. After configuration (priority=1, enable=1, threshold=0), IRQ fires. |
| 8 | + * 5. Claim register returns source ID 1 and clears pending. |
| 9 | + * 6. After claim, IRQ deasserted (no pending source above threshold). |
| 10 | + * |
| 11 | + * The test runs in M-mode. External interrupts are polled via meip |
| 12 | + * (mip.MEIP bit 11) since we haven't set up a trap handler here — we |
| 13 | + * just want to verify the PLIC logic drives the irq_external line. |
| 14 | + * |
| 15 | + * NOTE: UART RX loopback requires the board's RX pin to be wired back to |
| 16 | + * TX (or use a terminal that echoes). On Tang Nano 20K the UART goes to |
| 17 | + * the onboard USB-serial bridge which does NOT auto-echo, so we instead |
| 18 | + * test the PLIC register interface directly without requiring actual UART |
| 19 | + * traffic. The pending bit is verified by reading PLIC registers after |
| 20 | + * the UART RX fires (observed from a terminal sending a character). |
| 21 | + * |
| 22 | + * For a self-contained test (no terminal echo), we verify: |
| 23 | + * - Register R/W works correctly. |
| 24 | + * - IRQ output is masked by enable/threshold correctly. |
| 25 | + * - The claim/complete protocol clears pending. |
| 26 | + * |
| 27 | + * Run with picocom: type any character to trigger the PLIC source. |
| 28 | + */ |
| 29 | + |
| 30 | +#define UART_RX ((volatile unsigned int *)0x00030000) |
| 31 | +#define UART_TX ((volatile unsigned int *)0x00030004) |
| 32 | + |
| 33 | +/* PLIC base = 0x0C00_0000 */ |
| 34 | +#define PLIC_PRIO1 ((volatile unsigned int *)0x0C000004) |
| 35 | +#define PLIC_PENDING0 ((volatile unsigned int *)0x0C001000) |
| 36 | +#define PLIC_ENABLE0 ((volatile unsigned int *)0x0C002000) |
| 37 | +#define PLIC_THRESHOLD ((volatile unsigned int *)0x0C200000) |
| 38 | +#define PLIC_CLAIM ((volatile unsigned int *)0x0C200004) |
| 39 | + |
| 40 | +/* CSR helpers */ |
| 41 | +#define read_csr(reg) ({ unsigned int __v; \ |
| 42 | + __asm__ volatile ("csrr %0, " #reg : "=r"(__v)); __v; }) |
| 43 | +#define set_csr(reg, bit) __asm__ volatile ("csrs " #reg ", %0" :: "rK"(bit)) |
| 44 | +#define clear_csr(reg, bit) __asm__ volatile ("csrc " #reg ", %0" :: "rK"(bit)) |
| 45 | + |
| 46 | +#define MIP_MEIP (1u << 11) /* machine external interrupt pending */ |
| 47 | +#define MIE_MEIE (1u << 11) /* machine external interrupt enable */ |
| 48 | + |
| 49 | +static void uart_putc(unsigned char c) |
| 50 | +{ |
| 51 | + while (*UART_TX & 1); |
| 52 | + *UART_TX = c; |
| 53 | +} |
| 54 | + |
| 55 | +static void uart_puts(const char *s) |
| 56 | +{ |
| 57 | + while (*s) uart_putc((unsigned char)*s++); |
| 58 | +} |
| 59 | + |
| 60 | +static void uart_puthex(unsigned int v) |
| 61 | +{ |
| 62 | + const char *h = "0123456789ABCDEF"; |
| 63 | + uart_putc('0'); uart_putc('x'); |
| 64 | + for (int i = 28; i >= 0; i -= 4) |
| 65 | + uart_putc(h[(v >> i) & 0xF]); |
| 66 | +} |
| 67 | + |
| 68 | +static unsigned int pass, fail; |
| 69 | + |
| 70 | +static void check(const char *name, unsigned int got, unsigned int expected) |
| 71 | +{ |
| 72 | + if (got == expected) { |
| 73 | + uart_puts(" PASS "); uart_puts(name); uart_puts("\r\n"); |
| 74 | + pass++; |
| 75 | + } else { |
| 76 | + uart_puts(" FAIL "); uart_puts(name); |
| 77 | + uart_puts(" got="); uart_puthex(got); |
| 78 | + uart_puts(" exp="); uart_puthex(expected); |
| 79 | + uart_puts("\r\n"); |
| 80 | + fail++; |
| 81 | + } |
| 82 | +} |
| 83 | + |
| 84 | +int main(void) |
| 85 | +{ |
| 86 | + uart_puts("\r\n=== NyanSoC PLIC Test ===\r\n"); |
| 87 | + |
| 88 | + pass = 0; fail = 0; |
| 89 | + |
| 90 | + /* ── 1. Reset state ─────────────────────────────────────────────────── */ |
| 91 | + uart_puts("1. Reset state\r\n"); |
| 92 | + check("prio1=0", *PLIC_PRIO1, 0); |
| 93 | + check("pending0=0", *PLIC_PENDING0, 0); |
| 94 | + check("enable0=0", *PLIC_ENABLE0, 0); |
| 95 | + check("threshold=0", *PLIC_THRESHOLD, 0); |
| 96 | + check("claim=0", *PLIC_CLAIM, 0); |
| 97 | + |
| 98 | + /* ── 2. R/W registers ──────────────────────────────────────────────── */ |
| 99 | + uart_puts("2. Register R/W\r\n"); |
| 100 | + |
| 101 | + *PLIC_PRIO1 = 7; |
| 102 | + check("prio1=7", *PLIC_PRIO1, 7); |
| 103 | + *PLIC_PRIO1 = 0; |
| 104 | + |
| 105 | + *PLIC_ENABLE0 = 2; /* bit[1] = src1 */ |
| 106 | + check("enable=2", *PLIC_ENABLE0, 2); |
| 107 | + *PLIC_ENABLE0 = 0; |
| 108 | + |
| 109 | + *PLIC_THRESHOLD = 3; |
| 110 | + check("thr=3", *PLIC_THRESHOLD, 3); |
| 111 | + *PLIC_THRESHOLD = 0; |
| 112 | + |
| 113 | + /* ── 3. Pending from UART RX (requires terminal to send a byte) ────── */ |
| 114 | + uart_puts("3. Waiting for UART RX byte (send any char from terminal)...\r\n"); |
| 115 | + |
| 116 | + /* Enable UART RX interrupt in PLIC (priority=1, enable=1, threshold=0) */ |
| 117 | + *PLIC_PRIO1 = 1; |
| 118 | + *PLIC_ENABLE0 = 2; /* bit[1] */ |
| 119 | + *PLIC_THRESHOLD = 0; |
| 120 | + |
| 121 | + /* Enable machine external interrupts in mstatus/mie */ |
| 122 | + set_csr(mie, MIE_MEIE); |
| 123 | + |
| 124 | + /* Poll mip.MEIP — set by CPU when irq_external is asserted */ |
| 125 | + unsigned int waited = 0; |
| 126 | + while (!(read_csr(mip) & MIP_MEIP)) { |
| 127 | + waited++; |
| 128 | + if (waited == 0x4000000u) { |
| 129 | + uart_puts(" TIMEOUT waiting for IRQ\r\n"); |
| 130 | + fail++; |
| 131 | + goto summary; |
| 132 | + } |
| 133 | + } |
| 134 | + uart_puts(" IRQ asserted (mip.MEIP=1)\r\n"); |
| 135 | + check("pending_set", (*PLIC_PENDING0 >> 1) & 1, 1); |
| 136 | + |
| 137 | + /* ── 4. Claim ───────────────────────────────────────────────────────── */ |
| 138 | + uart_puts("4. Claim\r\n"); |
| 139 | + unsigned int claimed = *PLIC_CLAIM; |
| 140 | + check("claim_id=1", claimed, 1); |
| 141 | + |
| 142 | + /* ── 5. Post-claim: pending cleared, IRQ deasserted ───────────────── */ |
| 143 | + uart_puts("5. Post-claim state\r\n"); |
| 144 | + check("pending_clr", (*PLIC_PENDING0 >> 1) & 1, 0); |
| 145 | + /* Write complete */ |
| 146 | + *PLIC_CLAIM = claimed; |
| 147 | + /* IRQ should now be deasserted */ |
| 148 | + check("mip_cleared", (read_csr(mip) >> 11) & 1, 0); |
| 149 | + |
| 150 | +summary: |
| 151 | + uart_puts("\r\n=== Results: "); |
| 152 | + uart_puthex(pass); uart_puts(" passed, "); |
| 153 | + uart_puthex(fail); uart_puts(" failed ===\r\n"); |
| 154 | + if (fail == 0) |
| 155 | + uart_puts("*** ALL PASS ***\r\n"); |
| 156 | + else |
| 157 | + uart_puts("*** FAILURES ***\r\n"); |
| 158 | + |
| 159 | + uart_puts("=== DONE ===\r\n"); |
| 160 | + return 0; |
| 161 | +} |
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