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RTL: Fix SDRAM direct-map address decode and write/read FSM arbitration ci #63: Commit 109e7dc pushed by higuoxing
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Doc: Rewrite README with current project state ci #62: Commit a884a48 pushed by higuoxing
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Doc: Update TODO.md — UART loader done, Linux build WIP ci #61: Commit 87e3b22 pushed by higuoxing
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WIP: SW: Add Buildroot and Linux kernel configs for NyanSoC ci #60: Commit f2410aa pushed by higuoxing
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Firmware: Add UART loader and SDRAM instruction fetch ci #59: Commit 526241a pushed by higuoxing
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SW: Add OpenSBI as submodule + NyanSoC platform port ci #58: Commit 4bc348c pushed by higuoxing
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SW: Add OpenSBI as submodule + NyanSoC platform port ci #57: Commit bec5423 pushed by higuoxing
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7X: SoC: Add PLIC at 0x0C00_0000 (UART RX source, S-mode context) ci #56: Commit c7e4907 pushed by higuoxing
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nyanrv: Add S-mode privilege level (Phase 1) ci #55: Commit fdddbca pushed by higuoxing
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tangnano20k: Add CLINT and clint_test firmware ci #54: Commit 99571ef pushed by higuoxing
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tangnano20k: integrate SDRAM controller, add sdram_test firmware ci #53: Commit 2367a84 pushed by higuoxing
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sdspi: Fix formal verification ci #52: Commit 6bd9226 pushed by higuoxing
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Fix .gitignore. ci #51: Commit 11eb931 pushed by higuoxing
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sdspi: Implement working SD SPI controller with block read/write ci #50: Commit 01eef36 pushed by higuoxing
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Fix formal verification tests for sdspi. ci #49: Commit 0111944 pushed by higuoxing
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Fix README.md ci #48: Commit 5560a63 pushed by higuoxing
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Implement M-extension. ci #47: Commit 7133e33 pushed by higuoxing
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Add sdspi module. ci #46: Commit f9e1010 pushed by higuoxing
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Fix README.md. ci #45: Commit c5dc420 pushed by higuoxing
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Move sim/ into rtl/sim/ ci #44: Commit de1b12e pushed by higuoxing
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Rename sdram_ctrl to sdram_gw2ar and add example ci #43: Commit 94beacc pushed by higuoxing
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Add a new firmware 'echo'. ci #42: Commit 15634f7 pushed by higuoxing
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sdram_ctrl: Implement full read/write/refresh paths and fix bugs ci #41: Commit 4e28179 pushed by higuoxing
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Add README.md ci #40: Commit c82ffc6 pushed by higuoxing
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uart: Use synchronous reset in example modules ci #39: Commit 0fab0a0 pushed by higuoxing
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