Move sim/ into rtl/sim/

Update all Makefile paths, .gitignore, and README to reflect the
new location. Verified all 5 CPU simulation tests still pass.

Made-with: Cursor

Author: higuoxing

.gitignore

@@ -9,13 +9,13 @@ firmware/**/imem_init.vh
 firmware/**/imem_rom.vh
 firmware/**/imem_data_rom.vh
 
-# Simulation build artifacts (sim/sw/)
-sim/sw/*.elf
-sim/sw/*.hex
-sim/sw/*.vvp
-sim/sw/*.vcd
-sim/sw/*.dis
-sim/sw/imem.hex
+# Simulation build artifacts (rtl/sim/sw/)
+rtl/sim/sw/*.elf
+rtl/sim/sw/*.hex
+rtl/sim/sw/*.vvp
+rtl/sim/sw/*.vcd
+rtl/sim/sw/*.dis
+rtl/sim/sw/imem.hex
 
 # Formal verification generated checks
 formal/riscv-formal/cores/nyanrv/checks/

Makefile

@@ -36,10 +36,10 @@ help:
 
 .PHONY: sim sim-waves
 sim:
-	$(MAKE) -C sim/sw run
+	$(MAKE) -C rtl/sim/sw run
 
 sim-waves:
-	$(MAKE) -C sim/sw waves
+	$(MAKE) -C rtl/sim/sw waves
 
 # ── Formal verification ───────────────────────────────────────────────────────
 
@@ -80,4 +80,4 @@ firmware-clean:
 
 .PHONY: clean
 clean: board-clean firmware-clean
-	$(MAKE) -C sim/sw clean
+	$(MAKE) -C rtl/sim/sw clean

README.md

@@ -26,18 +26,19 @@ NyanSoC/
 │   ├── uart/
 │   │   ├── uart_tx.v     # UART transmitter
 │   │   └── uart_rx.v     # UART receiver
-│   └── gowin/
-│       └── sdram_gw2ar.v  # SDRAM controller for GW2AR embedded SDRAM
+│   ├── gowin/
+│   │   └── sdram_gw2ar.v  # SDRAM controller for GW2AR embedded SDRAM
+│   └── sim/
+│       ├── rtl/          # Simulation testbenches
+│       └── sw/           # RV32I assembly test suite (iverilog)
 ├── boards/
 │   └── tangnano20k/      # Tang Nano 20K top-level + P&R scripts (only supported board)
 ├── firmware/
 │   ├── blinky/           # LED blink (C)
 │   └── hello_world/      # "Hello, World!" over UART (C)
-├── formal/
-│   ├── nyanrv/           # riscv-formal config and wrapper for nyanrv
-│   └── Makefile          # Formal verification flow
-└── sim/
-    └── sw/               # RV32I assembly test suite (iverilog)
+└── formal/
+    ├── nyanrv/           # riscv-formal config and wrapper for nyanrv
+    └── Makefile          # Formal verification flow
 ```
 
 ## Memory map (Tang Nano 20K SoC)
@@ -88,7 +89,7 @@ make flash
 
 ## Simulation tests
 
-The `sim/sw/` test suite assembles RV32I programs with `riscv64-elf-gcc` and
+The `rtl/sim/sw/` test suite assembles RV32I programs with `riscv64-elf-gcc` and
 runs them under [Icarus Verilog](http://iverilog.icarus.com/):
 
 ```sh

sim/Makefile rtl/sim/Makefilesim/Makefile renamed to rtl/sim/Makefile

@@ -1,6 +1,6 @@
-PROJ_ROOT := ..
+PROJ_ROOT := ../..
 RTL       := $(PROJ_ROOT)/rtl
-SIM_RTL   := $(PROJ_ROOT)/sim/rtl
+SIM_RTL   := $(PROJ_ROOT)/rtl/sim/rtl
 
 .PHONY: all run_cpu run_uart clean
 

sim/rtl/nyanrv_irq_tb.v rtl/sim/rtl/nyanrv_irq_tb.vsim/rtl/nyanrv_irq_tb.v renamed to rtl/sim/rtl/nyanrv_irq_tb.v

@@ -1,5 +1,5 @@
 ##############################################################################
-# NyanSoC test suite - sim/sw/Makefile
+# NyanSoC test suite - rtl/sim/sw/Makefile
 #
 # Usage:
 #   make              - build all tests and run them with iverilog
@@ -27,13 +27,13 @@ LDFLAGS  := -T link.ld -march=rv32i_zicsr -mabi=ilp32 -nostartfiles -nostdlib \
              -Wl,--no-relax
 
 # Simulation sources (relative to repository root)
-PROJ_ROOT := ../..
-TB        := $(PROJ_ROOT)/sim/rtl/nyanrv_tb.v
+PROJ_ROOT := ../../..
+TB        := $(PROJ_ROOT)/rtl/sim/rtl/nyanrv_tb.v
 RTL       := $(PROJ_ROOT)/rtl/nyanrv.v
 ASM_DIR   := asm
 
 TESTS     := test_alu test_branch test_mem test_jump test_csr
-IRQ_TB    := $(PROJ_ROOT)/sim/rtl/nyanrv_irq_tb.v
+IRQ_TB    := $(PROJ_ROOT)/rtl/sim/rtl/nyanrv_irq_tb.v
 
 # Keep intermediate ELF files on build errors for easier debugging
 .PRECIOUS: %.elf