Bump cortex-m from 0.6.3 to 0.7.7

[dependabot]

Bumps cortex-m from 0.6.3 to 0.7.7.

Release notes

Sourced from cortex-m's releases.

v0.7.7

What's Changed

• cortex-m v0.7.7: add documentation for critical-section-single-core by @​adamgreig in rust-embedded/cortex-m#458

Full Changelog: rust-embedded/cortex-m@v0.7.6...v0.7.7

v0.7.6 - 2022-08-12

• Added critical-section-single-core feature which provides an implementation for the critical-section crate for single-core systems, based on disabling all interrupts. (#448)

v0.7.5

Deprecated

• the ptr() function on all peripherals register blocks in favor of the associated constant PTR (#386).

Changed

• The inline-asm feature no longer requires a nightly Rust compiler, but does require Rust 1.59 or above.

Fixed

• Fixed singleton!() statics sometimes ending up in .data instead of .bss (#364, #380). (Backported from upcoming 0.8 release).

v0.7.4 - 2021-12-31

Added

• Added support for additional DWT counters (#349)
  • CPI counter
  • Exception overhead counter
  • LSU counter
  • Folded-instruction counter
• Added DWT.set_cycle_count (#347).
• Added support for the Cortex-M7 TCM and cache access control registers. There is a feature cm7 to enable access to these (#352).
• Add derives for serde, Hash, and PartialOrd to VectActive behind feature gates for host-platform use (#363).
• Support host platforms besides x86_64 (#369).
• Added delay::Delay::with_source, a constructor that lets you specify the SysTick clock source (#374).

Fixed

• Fix incorrect AIRCR PRIGROUP mask (#338, #339).
• Fix nightly users of inline-asm breaking now that the asm macro is removed from the prelude (#372).

Deprecated

... (truncated)

Changelog

Sourced from cortex-m's changelog.

[v0.7.7] - 2023-01-03

• Add missing documentation for critical-section-single-core feature added in v0.7.6.

[v0.7.6] - 2022-08-12

• Added critical-section-single-core feature which provides an implementation for the critical-section crate for single-core systems, based on disabling all interrupts. (#448)

[v0.7.5] - 2022-05-15

Deprecated

• the ptr() function on all peripherals register blocks in favor of the associated constant PTR (#386).

Changed

• The inline-asm feature no longer requires a nightly Rust compiler, but does require Rust 1.59 or above.

Fixed

• Fixed singleton!() statics sometimes ending up in .data instead of .bss (#364, #380). (Backported from upcoming 0.8 release).

[v0.7.4] - 2021-12-31

Added

• Added support for additional DWT counters (#349)
  • CPI counter
  • Exception overhead counter
  • LSU counter
  • Folded-instruction counter
• Added DWT.set_cycle_count (#347).
• Added support for the Cortex-M7 TCM and cache access control registers. There is a feature cm7 to enable access to these (#352).
• Add derives for serde, Hash, and PartialOrd to VectActive behind feature gates for host-platform use (#363).
• Support host platforms besides x86_64 (#369).
• Added delay::Delay::with_source, a constructor that lets you specify the SysTick clock source (#374).

Fixed

• Fix incorrect AIRCR PRIGROUP mask (#338, #339).
• Fix nightly users of inline-asm breaking now that the asm macro is removed from the prelude (#372).

Deprecated

... (truncated)

Commits

• bb4a782 Merge #458
• 47398cc cortex-m v0.7.7: add documentation for critical-section-single-core
• 641e419 Merge #449
• df9a479 Prepare for v0.7.6
• dc539a9 Merge #448
• 9e8c8e7 Add implementation for critical-section 1.0.
• e0bfe3a Merge #441
• bba4f0f Swap cortex-m-semihosting to use asm instead of llvm_asm
• 45406f6 Prepare for cortex-m v0.7.5
• ed00f50 Merge #380
• Additional commits viewable in compare view

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