new components: cam and replacement #259

desmonddak · 2025-09-19T21:39:10Z

Description & Motivation

These are two components needed to build various kinds of cache memory.
First is a CAM which is a contents-addressable memory. It addresses memory by using a tag instead of an address.
It primarily returns a 'hit' but also the address of where it is found (we can work to make this optional).
The CAM also provides a standard write interface for populating the tags as data, using the line address.

Second is a Replacement module which is abstract and one kind of policy implemented; pseudoLRU. This will eventually be an optional Module passed into a Cache that can be used to modify a Cache with different way replacement policies.

Related Issue(s)

None.

Testing

Basic testing of the CAM to allow for simultaneous tag writes then tag lookups.

Backwards-compatibility

Is this a breaking change that will not be backwards-compatible? If yes, how so?

No.

Documentation

Does the change require any updates to documentation? If so, where? Are they included?

No.

removed wavedumper

mkorbel1

This is wonderful!

lib/src/memory/replacement_policy.dart

mkorbel1 · 2025-09-30T19:58:17Z

lib/src/memory/cam.dart

+  final int idWidth;
+
+  /// The "enable" bit for this interface, enabling a request.
+  Logic get en => port('en');


why do we need an enable bit?

To tell it to do the cam match. You are providing a tag in, and the en tells it to do a match and return the idx or data back. This is the same as a DataPortInterface providing an en and addr. Just replace those with en and tag.
You may not want it doing a match if you simply have the tag field set on the read port.

the enable is needed for a write, but if you're doing a read isn't it the same if we just always read whatever address is given? what do you mean "doing a match"? is this for power savings? the combo logic is there either way

Good point and simpler is better.

lib/src/memory/cam.dart

lib/rohd_hcl.dart

lib/src/memory/cache.dart

mkorbel1 · 2025-10-01T19:47:51Z

lib/src/memory/cam.dart

+
+/// An interface to a Content-Addressable Memory (CAM) that allows querying
+/// for tags and returns the index of the matching tag if found.
+class TagInterface extends Interface<DataPortGroup> {


but i only see it used in one way, and the write ports are DataPortInterfaces. Is there another place you're planning to use them?

mkorbel1 · 2025-10-01T19:48:58Z

lib/src/memory/cam.dart

+  final int idWidth;
+
+  /// The "enable" bit for this interface, enabling a request.
+  Logic get en => port('en');


the enable is needed for a write, but if you're doing a read isn't it the same if we just always read whatever address is given? what do you mean "doing a match"? is this for power savings? the combo logic is there either way

lib/src/memory/cam.dart

lib/src/memory/cache.dart

lib/src/arithmetic/floating_point/floating_point_adder.dart

doc/Module.md

lib/src/arithmetic/signals/fixed_point_logic.dart

lib/src/interfaces/ready_valid_interface.dart

lib/src/memory/cache/cached_request_response_channel.dart

mkorbel1 · 2025-11-05T15:24:23Z

lib/src/memory/csr/csr.dart

+    String? logicName,
+  }) : super(fields, name: logicName ?? config.name);
+
+  // Historically the CSR disallowed renaming because the architectural


@kimmeljo any concerns?

I can't recall if the instance config can override the name from the architectural config of a CSR. If it can, then I don't see why this change would be necessary as the logic name == instance name.

@desmonddak was there a specific reason you needed this?

Now I cannot remember why I needed this. Let me undo and figure out what demanded the name.

mkorbel1 · 2025-11-05T15:26:54Z

test/memory/cache/cached_request_response_channel_test.dart

these test files are getting pretty long. is there an opportunity to refactor a bit to reduce repetition by making some reusable infra?

The last checkin 104e6aa

you will see a major refactoring of the cache and channel testing.

…t policy

kimmeljo · 2025-12-17T18:15:33Z

lib/src/interfaces/request_response_channel_base.dart

What's the difference between this file and lib/src/interfaces/request_response_channel.dart?

Good catch. This file is supposed to be the structures and the abstract base class (API).
The other file is supposed to be just a wired passthrough implementation. I accidentally duplicated in the second file.

kimmeljo · 2025-12-17T18:36:44Z

lib/src/memory/cache/cached_request_response_channel.dart

Two suggestions here for the future (both of which we've discussed):

(1) It might be useful to create a "flavor" of this module that assumes strict ordering of responses relative to requests. Then, instead of a CAM (fully associative cache) to track ordering, we can simplify the HW a bit by using a FIFO. This has the added benefit at the API level of not requiring a unique ID on incoming requests.

(2) It might be useful to create a "flavor" of this module that has a register file instead of a full blown cache on the data side. This would more closely mirror the notion of hash table lookup in HW. The API might have to be different though because it would require explicit invalidation/eviction from the outside.

kimmeljo · 2025-12-17T18:38:58Z

lib/src/memory/cache/direct_mapped_cache.dart

More of a general question, but does the RegisterFile abstraction allow for use of things like SRAM? I can imagine in some cases we'll need an SRAM at least for the data portion. Maybe we just punt on this for now?

This is an important question. Right now our RegisterFile abstraction supports asynchronous reads and I don't believe SRAM timing will allow that. So this will impact microarchitecture choices because of the additional cycle.
I think TAG side requires multiple ports because the read and write ports need to do a tag match, so I think you are right: we will likely stay with flops on the TAG side, but we need to think about the data side being an actual SRAM.

kimmeljo · 2025-12-17T18:44:54Z

lib/src/memory/cache/set_associative_cache.dart

More of a nitpick, but isn't set associative the general term while fully associative/direct mapped are just special cases (ways=n, 1 respectively). Maybe worth consolidating into a single implementation?

Yes, this is absolutely true. I can try to consolidate, first at the API level, and then perhaps at the implementation level. ROHD is powerful enough to probably make this simple (like single 'way' array probably eliminates some logic signals).

kimmeljo · 2025-12-17T18:47:36Z

lib/src/memory/csr/csr.dart

+    String? logicName,
+  }) : super(fields, name: logicName ?? config.name);
+
+  // Historically the CSR disallowed renaming because the architectural


I can't recall if the instance config can override the name from the architectural config of a CSR. If it can, then I don't see why this change would be necessary as the logic name == instance name.

@desmonddak was there a specific reason you needed this?

kimmeljo · 2025-12-17T18:50:19Z

lib/src/memory/ready_valid_fifo.dart

This is awesome. I vaguely recall in the "regular" FIFO implementation that writeEnable when full and readEnable when empty can cause bad things to happen. I see you've handled that here. Is it worth handling that in the "regular" implementation too? Or am I misremembering?

I cannot remember if we built the bypasses there as well.
The reason it could be worth handling is things like skidbuffers (single entry FIFOs) that need to be depth 2 if you don't handle these bypass cases. There can be a lot of those that have to have a spare entry.
We need to check this (and make sure there is a clear test for these edge cases to ensure they never break.

kimmeljo · 2025-12-17T18:51:25Z

test/interfaces/apb_bfm_test.dart

Note: I am moving these tests in my axi branch to a different location. So maybe undo this change and I will deal with it on my side? Unless you really need it...

I will undo this. I do not think I need it.

new components: cam and replacement

05d77fe

desmonddak marked this pull request as draft September 19, 2025 21:39

desmonddak requested a review from mkorbel1 September 19, 2025 21:39

desmonddak added 19 commits September 23, 2025 15:09

test/memory added

41bf98e

smoke test for Cache working

be4dfbf

cleanup and more file moves

11f056f

updated code docs for cache

b1771d7

updated code docs for cache

fa52418

Cache passes a fill then read exhaustive test avoiding evictions

26bf9e2

Cache cleanup: still need to figure out TagRF valid bit storage

8513ff1

Cache cleanup -- use different interfaces for read vs write

6bf67b3

Cache cleanup -- remove vcd generation

e6ead6f

updated replacement to be cleaner

ac75a69

added valid-bit handling for tags

22432a1

forgot to remove wavedumper

853afe2

working with valid bit but not yet invalidating

b8a10fa

invalidate logic in, needs tests

08727d2

invalidate working

ff381bd

write to a hit, double-write tests

9ef67c2

Better SV output, cleaner ROHD

5f99bf4

Cleaner ROHD, should pass CI

3389438

Update cache_test.dart

104e6aa

removed wavedumper

mkorbel1 reviewed Sep 30, 2025

View reviewed changes

desmonddak added 2 commits September 30, 2025 15:49

better organization of cache files, cleanup of comments

b29d48c

use flop vs Sequential and reduce loops

ad869e5

mkorbel1 reviewed Oct 1, 2025

View reviewed changes

desmonddak added 4 commits October 1, 2025 14:14

better naming for the ReadCache

0637d7c

simplified rohd_hcl.dart and udpated cam to remove enable

0021f24

proposed Cache interface for handling evictions

d8b4a45

Merge branch 'main' into cache

79b755b

desmonddak added 4 commits October 13, 2025 13:06

Added Cache and Cam documentation

a48cc2b

pull the vcd generation

11c3d95

cache componentry

85a7966

doc update

f0a387b

desmonddak force-pushed the cache branch from 048e541 to f0a387b Compare October 17, 2025 21:53

desmonddak added 9 commits October 29, 2025 12:34

new caching components

2194e40

minor fixes that blocked CI

98c2d10

compute cache hit without request.valid

e9f01ba

directory reorg for cache components

8fe97c3

updated cache components with eviction, etc

a0694a8

add logicstructure components using new addTyped protocol

94c195a

better docs for caches

3aae40a

new primer on creating a good module

10aeb52

removed unused module

b0e5c84

mkorbel1 reviewed Nov 5, 2025

View reviewed changes

desmonddak added 6 commits November 5, 2025 17:09

combinational dependency ready->valid

d3b507f

cache configuration

1e0a5e6

cleanup

463a48d

major cache/channel test cleanup

ee4043e

put in cache and channel testing infrastructure to simplify tests

731de7f

forgot a WaveDumper

da67e5b

desmonddak requested a review from mkorbel1 November 9, 2025 16:55

ganewto and others added 6 commits November 9, 2025 12:14

minor change to check github access

8833dca

refactoring of cache testing and fixes for cache bugs, new replacemen…

ecf740f

…t policy

trailing space.

583354c

flutter confusion on .value

1807894

tests: remove duplicate direct-mapped cache test files (merged)

0d8a7d8

merged and cleaned up cache tests

85d745e

desmonddak marked this pull request as ready for review December 5, 2025 18:59

kimmeljo requested changes Dec 17, 2025

View reviewed changes

new components: cam and replacement #259

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new components: cam and replacement #259

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desmonddak commented Sep 19, 2025

Description & Motivation

Related Issue(s)

Testing

Backwards-compatibility

Documentation

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desmonddak Sep 30, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

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desmonddak Sep 30, 2025 •

edited

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