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Support Indirect ISR handling through zero page pointer address #11
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This is such a good idea! I have been using the Sixty5o2-bootloader for some time now but found it frustrating to be directed to using the NMI in the code I upload (I modified the vector in bootloader.asm, in the same fashion you did, but for NMI so I wouldn't mess with the bootloader itself). So I really like this PR! I noticed one minor detail in the updated readme that I think is incorrect. See the line here: a77de40#diff-1550ec65ac92f65817fc28928dfef526912b5f52356ff43651369bae92f56031R222 . It should read $05 in order to accommodate both high and low byte of the address if I understand your code correctly. |
No, 6502 is little endian so addresses are read low byte first. The jump instruction at the IRQ vector in bootloader is an indirect zero page jump. You must point it at the LSB in zero page. I have committed a working example with this PR. Try it out. |
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On reset the bootloader stores its own interrupt address (i.e. the value of the label "ISR") in bytes $04 and $05. So my point was that the Readme also should mention that $05 is used by the bootloader internally. As I said, it is a minor detail but has the potential to be confusing if not mentioned. By the way, I cloned it and gave it a try. It works like a charm! |
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Ah ok. I'll make the clarification and push a new commit. |
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@linuxplayground David, that's awesome. I always wanted to get that fixed. I think there is another way to solve it, and Ben's interrupt videos point to that ... but I'll check the PR on the weekend and merge it asap. Thanks a lot! |
This PR is to allow for user programs to define their own interrupt handling. The mod is quite simple.