firpfbch: enhanced the channelizer to support user-defined decimate delays #406
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Feature Update: Configurable Decimate Delay in FIR PFB Channelizer
I've enhanced the FIR polyphase filter bank (PFB) channelizer to support user-defined decimator delays, enabling flexible sample time shifting for timing recovery applications. Key improvements include:
Implementation Notes:
The original implementation represents a special case when delay=1. The new architecture preserves this behavior while expanding functionality through:
Revised FFT Input Order Explanation
Regarding the author's note in firpfbch.proto.c about reversed FFT inputs:
This reversal is fundamentally tied to the delay compensation mechanism when using FFT instead of IFFT.
For a channelizer decimator with delay n₀ samples, the phase compensation mechanism differs between IFFT/FFT implementations(the two are equivalent):
IFFT-based implementation requires: Right-circular shift input by n₀
FFT-based implementation (like ours) requires:
In our original implementation (delay n₀=1 special case):
IFFT requires 1-sample right shift
FFT equivalent needs 0 left shift after reversal (explaining the reversed order)
Practical Benefits of Configurable Delay
As emphasized by Fredric J. Harris in Digital Receivers and Transmitters Using Polyphase Filter Banks for Wireless Communications:
Future Roadmap
This pattern could extend to:
Would appreciate your guidance on these implementation decisions.