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arm-bsp/trusted-firmware-m: corstone1000: Multicore support for Corstone-1000 FVP
This changeset introduces the multicore support for the Corstone-1000 FVP. Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
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‎meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0013-platform-CS1000-Add-multicore-support-for-FVP.patch‎

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From 1120957e74a1a0727a215188813cab3e47602e71 Mon Sep 17 00:00:00 2001
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From: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
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Date: Thu, 9 May 2024 13:20:57 +0000
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Subject: [PATCH] platform: CS1000: Add multicore support for FVP
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This changeset adds the support to enable the secondary cores for
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the Corstone-1000 FVP
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Upstream-Status: Submitted [https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/29242]
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Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
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---
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.../target/arm/corstone1000/CMakeLists.txt | 6 +++
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.../corstone1000/Device/Config/device_cfg.h | 6 +++
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.../arm/corstone1000/tfm_hal_multi_core.c | 38 ++++++++++++++++++-
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3 files changed, 48 insertions(+), 2 deletions(-)
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diff --git a/platform/ext/target/arm/corstone1000/CMakeLists.txt b/platform/ext/target/arm/corstone1000/CMakeLists.txt
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index e2a7ac302..a269251aa 100644
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--- a/platform/ext/target/arm/corstone1000/CMakeLists.txt
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+++ b/platform/ext/target/arm/corstone1000/CMakeLists.txt
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@@ -374,6 +374,12 @@ target_sources(tfm_psa_rot_partition_ns_agent_mailbox
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tfm_hal_multi_core.c
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)
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+if (PLATFORM_IS_FVP)
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+target_compile_definitions(tfm_psa_rot_partition_ns_agent_mailbox
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+ PUBLIC
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+ $<$<BOOL:${ENABLE_MULTICORE}>:CORSTONE1000_FVP_MULTICORE>
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+)
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+endif()
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#========================= tfm_spm ============================================#
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target_sources(tfm_spm
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diff --git a/platform/ext/target/arm/corstone1000/Device/Config/device_cfg.h b/platform/ext/target/arm/corstone1000/Device/Config/device_cfg.h
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index 222905d3d..9d48f119e 100644
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--- a/platform/ext/target/arm/corstone1000/Device/Config/device_cfg.h
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+++ b/platform/ext/target/arm/corstone1000/Device/Config/device_cfg.h
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@@ -45,5 +45,11 @@
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/* CFI Controller */
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#define CFI_S
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+/* Total number of host cores */
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+#if CORSTONE1000_FVP_MULTICORE
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+#define PLATFORM_HOST_MAX_CORE_COUNT 4
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+#else
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+#define PLATFORM_HOST_MAX_CORE_COUNT 1
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+#endif
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#endif /* __DEVICE_CFG_H__ */
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diff --git a/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c b/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c
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index f0e2bc333..ce72e50c9 100644
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--- a/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c
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+++ b/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c
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@@ -11,9 +11,14 @@
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#include "tfm_hal_multi_core.h"
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#include "fwu_agent.h"
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-#define HOST_SYS_RST_CTRL_OFFSET 0x0
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+#define HOST_SYS_RST_CTRL_OFFSET 0x000
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+#define HOST_CPU_PE0_CONFIG_OFFSET 0x010
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+#define HOST_CPU_PE1_CONFIG_OFFSET 0x020
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+#define HOST_CPU_PE2_CONFIG_OFFSET 0x030
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+#define HOST_CPU_PE3_CONFIG_OFFSET 0x040
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+#define HOST_CPU_BOOT_MASK_OFFSET 0x300
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#define HOST_CPU_CORE0_WAKEUP_OFFSET 0x308
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-#define HOST_CPU_PE0_CONFIG_OFFSET 0x010
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+
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#define AA64nAA32_MASK (1 << 3)
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#ifdef EXTERNAL_SYSTEM_SUPPORT
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@@ -53,9 +58,29 @@ void tfm_hal_boot_ns_cpu(uintptr_t start_addr)
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volatile uint32_t *PE0_CONFIG =
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(uint32_t *)(CORSTONE1000_HOST_BASE_SYSTEM_CONTROL_BASE
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+ HOST_CPU_PE0_CONFIG_OFFSET);
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+#if CORSTONE1000_FVP_MULTICORE
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+ volatile uint32_t *PE1_CONFIG =
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+ (uint32_t *)(CORSTONE1000_HOST_BASE_SYSTEM_CONTROL_BASE
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+ + HOST_CPU_PE1_CONFIG_OFFSET);
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+ volatile uint32_t *PE2_CONFIG =
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+ (uint32_t *)(CORSTONE1000_HOST_BASE_SYSTEM_CONTROL_BASE
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+ + HOST_CPU_PE2_CONFIG_OFFSET);
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+ volatile uint32_t *PE3_CONFIG =
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+ (uint32_t *)(CORSTONE1000_HOST_BASE_SYSTEM_CONTROL_BASE
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+ + HOST_CPU_PE3_CONFIG_OFFSET);
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+ volatile uint32_t *CPU_BOOT_MASK =
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+ (uint32_t *)(CORSTONE1000_HOST_BASE_SYSTEM_CONTROL_BASE
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+ + HOST_CPU_BOOT_MASK_OFFSET);
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+ *CPU_BOOT_MASK = 0xf;
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+#endif
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/* Select host CPU architecture as AArch64 */
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*PE0_CONFIG |= AA64nAA32_MASK; /* 0b1 – AArch64 */
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+#if CORSTONE1000_FVP_MULTICORE
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+ *PE1_CONFIG |= AA64nAA32_MASK; /* 0b1 – AArch64 */
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+ *PE2_CONFIG |= AA64nAA32_MASK; /* 0b1 – AArch64 */
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+ *PE3_CONFIG |= AA64nAA32_MASK; /* 0b1 – AArch64 */
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+#endif
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/* wakeup CORE0 before bringing it out of reset */
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*reset_ctl_wakeup_reg = 0x1;
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@@ -63,6 +88,15 @@ void tfm_hal_boot_ns_cpu(uintptr_t start_addr)
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/* Clear HOST_SYS_RST_CTRL register to bring host out of RESET */
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*reset_ctl_reg = 0;
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+#if CORSTONE1000_FVP_MULTICORE
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+ /* Wake up secondary cores.
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+ * This should be done after bringing the primary core out of reset. */
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+ for(int core_index=1; core_index < PLATFORM_HOST_MAX_CORE_COUNT; core_index++)
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+ {
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+ *reset_ctl_wakeup_reg = (0x1 << core_index);
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+ }
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+#endif
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+
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(void) start_addr;
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#ifdef EXTERNAL_SYSTEM_SUPPORT
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--
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2.34.1
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‎meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m-corstone1000.inc‎

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@@ -29,6 +29,7 @@ SRC_URI:append:corstone1000 = " \
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file://0010-CC312-alignment-of-cc312-differences-between-fvp-and.patch \
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file://0011-Platform-corstone1000-Increase-buffers-for-EFI-vars.patch \
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file://0012-corstone1000-Remove-reset-after-capsule-update.patch \
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file://0013-platform-CS1000-Add-multicore-support-for-FVP.patch \
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"
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# TF-M ships patches for external dependencies that needs to be applied

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