This project contains a complete computing stack built from scratch — a two-pass RISC-V assembler that converts assembly to binary with a ~100% accuracy; a RISC-V simulator that executes those binaries with full signed/unsigned arithmetic, memory, and branch semantics — with a ~100% accuracy; a bare-metal RISC-V kernel that boots on QEMU, drives UART via memory-mapped I/O, manages heap memory with a page-based free list, runs multiple processes, and switches between them preemptively using timer interrupts and a trap handler that saves and restores all 32 registers; and a C compiler with a hand-written lexer, recursive-descent parser that produces an AST, and a code generator targeting RISC-V assembly — supporting integers, variables, binary arithmetic, if/else, while loops, and return statements. Every layer feeds the next: C source → compiler → assembly → assembler → binary → simulator or kernel on QEMU. The above statistics mentioned about the Assembler and Simulator were based on autograding infrastructure by respective IIITD Officials.
just as an example : below is a proof of 2 pipelines integrating :
initial set of instructions given to compiler
compiler->assembler->kernel
compiler->assembler->simulator
It isn't a one day project (based on the commit history) below are the details : The assembler was started around 2-3 weeks prior 16th of March, it was completed and evaluated by officials assigned on 16th of March. (though some minor modifications like adding more instructions necessary were added later on in May) The simulator was started around 2-3 weeks prior 23rd of April, it was completed and evaluated by officials assigned on 23rd of April. (again as above, minor modifications lasted till the end of May.) The compiler and kernel were my major add-ons to the project on which i worked from 10th of May till 14th of June.
(the project isn't completed yet) Thanks for visiting :)