Verification of an Arithmetic Logic Unit (ULA/ALU) capable of performing 7 operations
The project was developed using the EDA Playground tool (which is free to use) based on the Metric Driven Verification technique which has 4 steps: Planning, construction of a verification environment based on Randomization, execution of test scenarios, and measurement/process analysis (Coverage). The environments are built using the UVM methodology in SystemVerilog language.