[Verilator] Build failure due to typo in testbench/testbench.v signal connection

[ScottaMcdonald]

Description

I encountered a build failure when attempting to compile the RTL simulation model using Verilator. The issue appears to be caused by a typo in the testbench module instantiation within testbench/testbench.v.

The signal connected to the .raddr port is named imem_addr_i, but the declared wire in the local scope is named imem_raddr_i. This causes Verilator to throw IMPLICIT, WIDTHEXPAND, and UNDRIVEN warnings/errors, leading to a failed build.

Steps to Reproduce

cd sim
make clean
make verilator=1 rv32c=1 rv32e=1 rv32b=1

Error log

%Warning-IMPLICIT: ../rtl/../testbench/testbench.v:399:17: Signal definition not found, creating implicitly: 'imem_addr_i'
                                                         : ... Suggested alternative: 'imem_raddr_i'
  399 |         .raddr (imem_addr_i),
      |                 ^~~~~~~~~~~
%Warning-WIDTHEXPAND: ../rtl/../testbench/testbench.v:399:10: Input port connection 'raddr' expects 31 bits on the pin connection, but pin connection's VARREF 'imem_addr_i' generates 1 bits.
      |                 ^~~~~
%Warning-UNDRIVEN: ../rtl/../testbench/testbench.v:399:17: Signal is not driven: 'imem_addr_i'
      |                 ^~~~~~~~~~~
%Error: Exiting due to 3 warning(s)
make: *** [Makefile:72: sim] Error 1

Analysis

In testbench/testbench.v, the wire is declared correctly as:

wire [29: 0] imem_raddr_i;

However, in the instantiation of the testbench module (around line 399), it is referenced incorrectly:

.raddr (imem_addr_i),

Suggested Fix

Update line 399 in testbench/testbench.v to use the correct signal name imem_raddr_i.

--- a/testbench/testbench.v
+++ b/testbench/testbench.v
@@ -396,7 +396,7 @@
         .clk   (clk),
         .rst   (rst),
         .addr  (imem_addr),
-        .raddr (imem_addr_i),
+        .raddr (imem_raddr_i),
         .waddr (imem_waddr),
         .rdata (imem_rdata),
         .wdata (imem_wdata),