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<code>csrrci</code> with uimm=0 on read-only CSR (time) incorrectly raises Illegal Instruction exception

Status: Open.

#17 In kuopinghsu/srv32;

· YzhDDDing opened on Dec 28, 2025

Srv32 does not raise Illegal Instruction for csrrc write attempt to read-only <code>instret</code> CSR (Spike traps with mcause=2)

Status: Open.

#16 In kuopinghsu/srv32;

· ScottaMcdonald opened on Dec 27, 2025

[Bug Report] <code>cycle</code> CSR: Missing Illegal Instruction Exception on write attempt via csrrsi

Status: Open.

#15 In kuopinghsu/srv32;

· YzhDDDing opened on Dec 27, 2025

[Verilator] Build failure due to typo in testbench/testbench.v signal connection

Status: Open.

#14 In kuopinghsu/srv32;

· ScottaMcdonald opened on Dec 15, 2025

Implementing RV32C instruction

Status: Open.

#5 In kuopinghsu/srv32;

· WeiCheng14159 opened on Dec 31, 2020

Run modified xv6 for RV32I

Status: Open.

#3 In kuopinghsu/srv32;

· jserv opened on Sep 21, 2020