[TransferEngine][ROCm] Add HIP dmabuf MR registration for AMD GPUs (fixes #751)#2225
[TransferEngine][ROCm] Add HIP dmabuf MR registration for AMD GPUs (fixes #751)#2225andyluo7 wants to merge 8 commits into
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Code Review
This pull request introduces support for HIP dmabuf memory registration in the RDMA transport layer when USE_HIP is enabled, mirroring the existing CUDA dmabuf path. It links the hsa-runtime64 library and utilizes hsa_amd_portable_export_dmabuf to export device memory allocations. The review feedback highlights a potential issue in multi-GPU environments where background threads might not have the correct HIP device context active when calling hipMemGetAddressRange. It is recommended to use an RAII guard to temporarily set and restore the active HIP device context to ensure reliable address range queries.
| } else if (hipAttr.type == hipMemoryTypeDevice || | ||
| hipAttr.type == hipMemoryTypeManaged) { | ||
| // Device memory — use dmabuf fd export + ibv_reg_dmabuf_mr(). | ||
| // Get the allocation base + size, since `addr` may sit at an offset | ||
| // within a larger hipMalloc block (caching allocators pack tensors). | ||
| hipDeviceptr_t allocBase = nullptr; | ||
| size_t allocSize = 0; | ||
| hipRes = hipMemGetAddressRange( | ||
| &allocBase, &allocSize, reinterpret_cast<hipDeviceptr_t>(addr)); |
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In multi-GPU environments, background worker threads (such as RDMA polling/worker threads) may not have an active HIP device context initialized, or may have the wrong device context active. Calling hipMemGetAddressRange without ensuring the correct device context is active can lead to failures or incorrect address range queries.
To prevent this, we should set the active HIP device to hipAttr.device before calling hipMemGetAddressRange, and restore the previous device context afterwards using an RAII guard.
} else if (hipAttr.type == hipMemoryTypeDevice ||
hipAttr.type == hipMemoryTypeManaged) {
struct DeviceGuard {
int oldDevice = 0;
bool restore = false;
bool setSuccess = false;
DeviceGuard(int newDevice) {
if (hipGetDevice(&oldDevice) == hipSuccess) {
restore = true;
}
setSuccess = (hipSetDevice(newDevice) == hipSuccess);
}
~DeviceGuard() {
if (restore) {
hipSetDevice(oldDevice);
}
}
} devGuard(hipAttr.device);
if (!devGuard.setSuccess) {
LOG(ERROR) << "Failed to set HIP device to " << hipAttr.device;
return ERR_CONTEXT;
}
// Device memory — use dmabuf fd export + ibv_reg_dmabuf_mr().
// Get the allocation base + size, since `addr` may sit at an offset
// within a larger hipMalloc block (caching allocators pack tensors).
hipDeviceptr_t allocBase = nullptr;
size_t allocSize = 0;
hipRes = hipMemGetAddressRange(
&allocBase, &allocSize, reinterpret_cast<hipDeviceptr_t>(addr));
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Build verification on AMD MI355X (AAC1, ROCm 7.2.2, atom-dev container): Full Mooncake tree built clean with this PR + ``` $ nm -D libtransfer_engine.so | grep -E 'hsa_amd_portable_export_dmabuf|hipPointerGetAttributes|hipMemGetAddressRange|ibv_reg_dmabuf_mr' Confirms:
The build also surfaced a pre-existing operator-precedence warning at `transfer_engine_impl.cpp:315` (`suggest parentheses around '&&' within '||'`) — untouched by this PR, mentioning here just for visibility. Next: end-to-end SGLang+Mooncake DSR1 disagg sweep on AAC1 MI355X with this patched binary, vs the current DRAM-staging workaround baseline (527 tok/s @ c=16, 160/160). Will post numbers as a follow-up comment. |
andyluo7
requested review from
alogfans,
chestnut-Q and
doujiang24
as code owners
T3 end-to-end PASS on AMD MI355X + Pensando ionicVerified the patch works in Mooncake's real Python call path on AAC1. Setup: ported this PR's HIP branch onto the older Mooncake bundled in `lmsysorg/sglang-rocm:v0.5.10.post1-rocm720-mi35x-20260503` (v0.3.7.post2, commit b6a841d). Same logical change; trivial idiom adjustment for the older `#if !defined(WITH_NVIDIA_PEERMEM) && defined(USE_CUDA)` umbrella. Rebuilt the `engine` pybind11 module and verified the new `engine.cpython-310-x86_64-linux-gnu.so` (24.5 MB) now links all four new symbols correctly: ``` Test: small Python script that initializes a TransferEngine over P2PHANDSHAKE (no etcd), allocates a 256 MiB torch tensor on `cuda:0` (which is `hipMemoryTypeDevice` on MI355X), then calls `engine.register_memory(ptr, size)`: ``` The same call on the stock build fails with the `EINVAL` reported in #751, because the `WITH_NVIDIA_PEERMEM=ON` default routes GPU memory through plain `ibv_reg_mr()`, which the ionic kernel driver rejects without an AMD peermem equivalent. The new HIP branch takes the `hsa_amd_portable_export_dmabuf` -> `ibv_reg_dmabuf_mr` path instead — and it works. Validation matrix recap
Patch is functionally correct end-to-end on real AMD hardware. Ready for review. — Note on the side: a single internal `Cannot allocate memory [12]` log appeared during the engine's own auxiliary buffer registration before the test buffer. This is unrelated to the dmabuf path (different address, ENOMEM not EINVAL) and the test buffer registration succeeded. Will investigate separately if it points to a real issue. |
Fixes kvcache-ai#751. Adds a parallel `#elif defined(USE_HIP)` branch in RdmaContext::registerMemoryRegionInternal that mirrors the existing CUDA dmabuf path (added by kvcache-ai#704) using ROCm's `hsa_amd_portable_export_dmabuf()` instead of `cuMemGetHandleForAddressRange(...DMA_BUF_FD...)`. This lets Mooncake register AMD GPU memory for RDMA without requiring an nvidia-peermem-equivalent kernel module — the path UCX's ROCm backend (uct/rocm/base/rocm_base.c) already uses successfully. Same host-vs-device split as the CUDA branch: `hipPointerGetAttributes` detects host memory and falls back to `ibv_reg_mr`; device/managed memory goes through the dmabuf path. `hipMemGetAddressRange` is used to get the true allocation base because `addr` may sit at an offset within a larger hipMalloc block (caching allocators pack tensors). CMake: added `hsa-runtime64` to the HIP link line in mooncake-transfer-engine/src/CMakeLists.txt. Validation: - Standalone dmabuf probe verified PASS on: * AMD MI355X (gfx950) + Pensando ionic + ROCm 7.2.2 * AMD MI300X (gfx942) + Broadcom Thor2 (bnxt_re) + ROCm 7.0.2 Probe source + container recipe: https://github.com/andyluo7/dynamo/blob/amd-poc-consumer-polish/amd-mi355x-poc/advanced/debug-probes/dmabuf_register_probe.cpp - Standalone compile check confirms all HIP/HSA/ibverbs symbols in the new branch resolve and link cleanly with hsa-runtime64 + libibverbs. End-to-end SGLang+Mooncake disagg validation (T3) on MI355X+ionic will follow in a comment once a full Mooncake build with submodules completes. CC @misterwilliam @stmatengss @alogfans (active on kvcache-ai#751) Closes kvcache-ai#751 Signed-off-by: Andy Luo <anluo@amd.com>
Linker on AAC1 atom-dev container failed with 'cannot find -lhsa-runtime64' because /opt/rocm/lib isn't on the default ld search path. Use find_library to locate libhsa-runtime64.so inside the ROCm install explicitly. ROCm_VERSION fallback handles non-symlinked installs. Signed-off-by: Andy Luo <anluo@amd.com>
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Codecov Report✅ All modified and coverable lines are covered by tests. 📢 Thoughts on this report? Let us know! |
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Quick note on the `test-wheel-ubuntu` failure — looks unrelated to this PR. Single test failed in 1 of 4 OS/Python combos (the other 3 cascade-cancelled): ``` This exercises the Mooncake Store over TCP, neither of which is touched by this PR (we only modify Transfer Engine's RDMA dmabuf MR registration). The test name + error pattern suggest a teardown-race condition (`test_client_tear_down` tears a client down and then puts). The same job (`test-wheel-ubuntu (ubuntu-24.04, 3.12)`) passed on the most recent main-branch run #26401719560, so it's not a chronic infra issue either — looks flaky. Happy to re-trigger or rebase onto a fresh main if helpful. The 11 other CI checks pass; Codecov confirms all modified lines are covered. |
| find_library(HSA_RUNTIME_LIBRARY | ||
| NAMES hsa-runtime64 | ||
| PATHS /opt/rocm/lib /opt/rocm-${ROCM_VERSION}/lib | ||
| REQUIRED) |
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Does rocm installer force to use this path?
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Good catch — /opt/rocm/lib was a hard-coded fallback that doesn't work for HPC installs / DKMS layouts / custom prefixes.
Pushed 40f6f97 to switch to:
find_package(hsa-runtime64 CONFIG REQUIRED)
target_link_libraries(transfer_engine PUBLIC hip::host hsa-runtime64::hsa-runtime64 rt)ROCm ships hsa-runtime64-config.cmake (confirmed at /opt/rocm/lib/cmake/hsa-runtime64/ on ROCm 7.0.2 and 7.2.2 in our two test clusters), and CMAKE_PREFIX_PATH already includes ROCm's cmake dir per common.cmake:279. No paths hard-coded now.
Per @alogfans review: "Does rocm installer force to use this path?" The previous patch hard-coded /opt/rocm/lib via find_library PATHS, which isn't portable across HPC installs or DKMS layouts. Switch to find_package(hsa-runtime64 CONFIG REQUIRED), which resolves against CMAKE_PREFIX_PATH (already includes ROCm's cmake dir per common.cmake:279) and uses the canonical hsa-runtime64::hsa-runtime64 imported target. No paths hard-coded. Signed-off-by: Andy Luo <anluo@amd.com>
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@alogfans — addressed both review points; replied inline + summarizing here for visibility. 1. `CMakeLists.txt` — "Does rocm installer force to use this path?" — No, that hard-coded find_package(hsa-runtime64 CONFIG REQUIRED)
target_link_libraries(transfer_engine PUBLIC hip::host hsa-runtime64::hsa-runtime64 rt)ROCm ships 2. `rdma_context.cpp:430` — "I didn't find any dereg function related to dmabuf_mr" — None needed: The only special thing about dmabuf is the fd lifecycle: the kernel Branch state: 3 small commits (original + 2 fixups), all signed off. T1/T2/T3 validation still PASS end-to-end on AAC1 MI355X + ionic. Happy to squash on merge if you'd prefer. |
…UF_MOVE_NOTIFY The previous version of this PR could silently succeed at `ibv_reg_dmabuf_mr` on a kernel without CONFIG_PCI_P2PDMA / CONFIG_DMABUF_MOVE_NOTIFY (e.g. Ubuntu 22.04 stock 5.15), then have subsequent RDMA transfers fail or mis-route — the kernel can't carry the dmabuf fd through PCIe peer-to-peer DMA without those options. Registration-side validation alone is hollow. Add an `isKernelDmabufSupported()` helper that mirrors RCCL's check at `projects/rccl/src/misc/rocmwrap.cc:266`: - Scans /boot/config-*, /usr/src/linux*/.config, etc. for the two CONFIG_ symbols, with /proc/kallsyms (pci_p2pdma, dma_buf_move_notify) as fallback when the kernel config file isn't readable. - Cached after the first call (static initializer). - Logs a clear warning when the check fails. When unsupported, fall back to `ibv_reg_mr` — same path the CUDA branch uses when nvidia-peermem is absent. The fallback is honest: it surfaces the registration failure at registration time, not mid-transfer. Distros that ship both options enabled by default: Ubuntu 24.04 (5.15 HWE -> 6.8), RHEL 9.4+, mainline kernel >= 6.x. Ubuntu 22.04 stock 5.15 lacks them — users on that combo need a kernel rebuild OR use the host-staged path (which Mooncake already supports). Signed-off-by: Andy Luo <anluo@amd.com>
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Important update — added a kernel-feature gate in `3308bac`. The gap: as-originally-submitted, this PR could let `ibv_reg_dmabuf_mr` succeed on a kernel without `CONFIG_PCI_P2PDMA` / `CONFIG_DMABUF_MOVE_NOTIFY` (e.g. stock Ubuntu 22.04 / 5.15) — and then have subsequent RDMA transfers silently fail or mis-route, because the kernel can't carry the dmabuf fd through PCIe peer-to-peer DMA without those options. My earlier T1/T3 PASS evidence verified MR registration succeeds but did not exercise an actual transfer, so it didn't catch this. Empirical verification on our two test clusters (run today after a colleague flagged the dependency):
So our previous "PASS on both clusters" claim was technically wrong for Hotaisle. AAC1 was always fine. The fix (`3308bac`): a static-init kernel-feature check that mirrors RCCL's at `projects/rccl/src/misc/rocmwrap.cc:266` — scans /boot/config-, /usr/src/linux/.config, /proc/kallsyms for the two required symbols. When unsupported:
Distros known to ship both options: Ubuntu 24.04 (5.15 HWE → 6.8), RHEL 9.4+, mainline kernels >= 6.x. Ubuntu 22.04 stock 5.15 lacks them; users on that combo either need a kernel rebuild or should stick with the host-staged path Mooncake already supports. Other refactors stay in place (RAII HipDeviceGuard from gemini's review; `find_package(hsa-runtime64 CONFIG)` per @alogfans). Branch state: 4 small commits, all signed off. |
typos CI tool flagged 'mis' as a partial word in the hyphenated forms;
both are valid as unhyphenated compounds ('misbehave', 'misroute').
Signed-off-by: Andy Luo <anluo@amd.com>
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Two CI failures after the typo fix — short analysis: `Spell Check with Typos`: ✅ fixed in `c28da96` (`mis-behave` → `misbehave`, `mis-route` → `misroute`). `build-flags (3.10)` / `(3.12)`: Tests pass cleanly, then LSan crashes at process teardown of the Rust `mooncake_store` test binary: ``` Looks unrelated to this PR's changes:
Could a maintainer re-trigger `build-flags` for me? Happy to dig deeper if it reproduces. |
Thank you for your contribution! I have re-triggered the CI test. |
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Thanks @stmatengss — |
| // Tested on: | ||
| // - AMD MI355X (gfx950) + Pensando ionic, ROCm 7.2.2 | ||
| // - AMD MI300X (gfx942) + Broadcom Thor2 (bnxt_re), ROCm 7.0.2 |
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Not sure that such details are needed in the code. Please consider compressing comments
| // CONFIG_PCI_P2PDMA=y | ||
| // CONFIG_DMABUF_MOVE_NOTIFY=y | ||
| // | ||
| // Mirrors RCCL's check at projects/rccl/src/misc/rocmwrap.cc:266 and the |
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Please remove path to the RCCL code. This path will quickly become outdated
| # CMake config that ROCm ships (resolved against CMAKE_PREFIX_PATH, | ||
| # which already includes the ROCm cmake dir per common.cmake), so the | ||
| # ROCm install location isn't hard-coded here. |
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Please remove this part of the comment. It does not contain any useful information
| # CMake config that ROCm ships (resolved against CMAKE_PREFIX_PATH, | ||
| # which already includes the ROCm cmake dir per common.cmake), so the | ||
| # ROCm install location isn't hard-coded here. | ||
| find_package(hsa-runtime64 CONFIG REQUIRED) |
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it makes hsa-runtime64 a hard build dependency for every USE_HIP=ON build. Please consider adding new Cmake option USE_HIP_DMABUF (default ON when ROCm is found) so users can disable it
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Adding environment variable to disable dmabuf usage in runtime also could be useful
| mrMeta.addr = addr; | ||
| mrMeta.mr = ibv_reg_mr(pd_, addr, length, access); | ||
| } else if (hipAttr.type == hipMemoryTypeDevice || | ||
| hipAttr.type == hipMemoryTypeManaged) { |
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is it safe to use dmabuf for managed memory? Managed pages can migrate between host and device, and the exported dmabuf fd captures the device-side handle only at export time
…GPUs Address amd-arozanov review: - CMakeLists: add USE_HIP_DMABUF option (default ON, auto-disabled if hsa-runtime64 not found); makes hsa-runtime64 an optional not hard dep - CMakeLists/rdma_context: gate all dmabuf code on USE_HIP_DMABUF instead of USE_HIP; trim verbose comments - rdma_context: add MOONCAKE_DISABLE_HIP_DMABUF env var for runtime opt-out - rdma_context: handle hipMemoryTypeManaged explicitly — fall back to ibv_reg_mr() since hsa_amd_portable_export_dmabuf captures device-side handle at export time; stale after page migration Signed-off-by: Andy Luo <andy.luo@amd.com>
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@amd-arozanov — thanks for the thorough review. Addressed all 6 points in fixup commit `2c5c3b8`: 1. 2. 3. 4. option(USE_HIP_DMABUF "Enable HIP dmabuf RDMA MR registration" ON)
if(USE_HIP_DMABUF)
find_package(hsa-runtime64 CONFIG) # QUIET — not REQUIRED
if(hsa-runtime64_FOUND)
target_compile_definitions(... USE_HIP_DMABUF)
target_link_libraries(... hsa-runtime64::hsa-runtime64)
endif()
endif()All dmabuf code in 5. 6. |
CI's Check code format step (clang-format-20, Google style, ColumnLimit 80) flagged rdma_context.cpp lines 71 and 450 as 83 chars. Wrap both per Google style to keep the diff minimal. Co-Authored-By: Claude Sonnet 4 <noreply@anthropic.com>
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Status update — ready for another look: @alogfans — would appreciate a re-review when you have a moment. Since your last pass on 2026-05-26, this PR has picked up:
@stmatengss — CI Gate is red but all three failing checks are broken on
Is the wheel test matrix being looked at upstream? Happy to help if it's a real bug, but this PR shouldn't need to gate on it. Could the merge gate be unblocked given the unrelated infra-level failures? |
I think it is a bug in the main stream but already fixed, and please merge with main. |
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@stmatengss thanks — merged |
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@stmatengss Post-merge CI completed. Build matrix is much better now: ✅ The failing test is in TEST_F(PromotionOnHitTest, AllocStartRejectsReapedTask) {
config.put_start_release_timeout_sec = 1;
...
std::this_thread::sleep_for(std::chrono::seconds(2));
auto alloc = service->PromotionAllocStart(...);
ASSERT_FALSE(alloc.has_value()) // depends on reaper having runNo RDMA, no dmabuf, no transfer-engine — purely the master service's in-memory promotion task tracking, which this PR doesn't touch. Could you re-trigger |
5 participants
Summary
Fixes #751.
Adds a parallel `#elif defined(USE_HIP)` branch in `RdmaContext::registerMemoryRegionInternal` that mirrors the existing CUDA dmabuf path (added by #704) using ROCm's `hsa_amd_portable_export_dmabuf()` instead of `cuMemGetHandleForAddressRange(...DMA_BUF_FD...)`.
This lets Mooncake register AMD GPU memory for RDMA without requiring an `nvidia-peermem`-equivalent kernel module — the same path UCX's ROCm backend (`uct/rocm/base/rocm_base.c`) already uses successfully on AMD ionic + Mellanox + Broadcom NICs.
Approach
`hipMemGetAddressRange` is used to get the true allocation base because the registration address may sit at an offset within a larger `hipMalloc` block (caching allocators pack tensors). The dmabuf offset returned by HSA is added to that base offset.
The CUDA branch (and its `Environ::Get().GetWithNvidiaPeermem()` opt-out) is unchanged.
Files changed
Validation
T1 — Standalone dmabuf probe
Exercises the exact same call sequence (`hipMalloc` → `hsa_amd_portable_export_dmabuf` → `ibv_reg_dmabuf_mr`) outside Mooncake to confirm the underlying RDMA stack works on each platform. Source + container recipes: `andyluo7/dynamo/.../dmabuf_register_probe.cpp`.
Two GPU generations × two NIC vendors → strong cross-platform evidence the dmabuf path is sound on AMD.
T2 — Standalone compile check of the new branch
The exact code added in this PR's HIP branch compiles + links cleanly with `hipcc -lhsa-runtime64 -libverbs` on Hotaisle. Confirms all symbols resolve.
T3 — End-to-end with SGLang+Mooncake disagg
Will follow as a comment on this PR once a full Mooncake submodule build completes on AAC1. Target: stock SGLang+Mooncake DSR1 disagg (no DRAM-staging workaround) running clean on MI355X + ionic, with concurrency sweep numbers.
Risks / known limitations
CC
@misterwilliam @stmatengss @alogfans — active on #751 and the CUDA dmabuf work. The "no ROCm hardware" blocker raised in #751 is no longer a constraint here — we developed against MI355X (AAC1) and MI300X (Hotaisle) and can run any additional validation you'd like.
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