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Merge pull request #741 from trabucayre/brs_100_gw1nr9
brisbaneSilicon BRS-100 GW1NR9
2 parents 87307de + 33751ce commit 2849917

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‎README.md‎

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├── berkeleylab_marble
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├── berkeleylab_obsidian
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├── bochenjingxin_kintex7_basec
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├── brisbaneSilicon_brs_100_gw1nr9
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├── camlink_4k
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├── colognechip_gatemate_evb
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├── colorlight_5a_75x

‎docs/boards_inventory.md‎

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| `berkeleylab_marble` | berkeleylab_marble | vivado | `125000000.0` | Ethernet, Etherbone | included |
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| `berkeleylab_obsidian` | berkeleylab_obsidian | vivado | `125000000.0` | Ethernet, Etherbone | included |
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| `bochenjingxin_kintex7_basec` | bochenjingxin_kintex7_basec | vivado | `125000000.0` | - | included |
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| `brisbaneSilicon_brs_100_gw1nr9` | brisbaneSilicon_brs_100_gw1nr9 | gowin | `27000000.0` | - | included |
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| `camlink_4k` | camlink_4k | trellis | `81000000.0` | - | included |
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| `colognechip_gatemate_evb` | colognechip_gatemate_evb | colognechip | `24000000.0` | SDCard, SPI SDCard, SPI Flash | included |
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| `colorlight_5a_75x` | colorlight_5a_75b, colorlight_5a_75e, colorlight_i5a_907 | trellis | `60000000.0` | Ethernet, Etherbone, SPI Flash | included |

‎litex_boards/platforms/brisbaneSilicon_brs_100_gw1nr9.py‎

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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2026 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.build.generic_platform import *
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from litex.build.gowin.platform import GowinPlatform
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from litex.build.openfpgaloader import OpenFPGALoader
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk27", 0, Pins("52"), IOStandard("LVCMOS33"), Misc("PULL_MODE=UP")),
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# Leds
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("user_led_n", 0, Pins("16"), Misc("PULL_MODE=UP DRIVE=8")),
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("user_led_n", 1, Pins("15"), Misc("PULL_MODE=UP DRIVE=8")),
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("user_led_n", 2, Pins("14"), Misc("PULL_MODE=UP DRIVE=8")),
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("user_led_n", 3, Pins("13"), Misc("PULL_MODE=UP DRIVE=8")),
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("user_led_n", 4, Pins("11"), Misc("PULL_MODE=UP DRIVE=8")),
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("user_led_n", 5, Pins("10"), Misc("PULL_MODE=UP DRIVE=8")),
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# Buttons
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("user_btn_n", 0, Pins("3"), Misc("PULL_MODE=UP")),
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("user_btn_n", 1, Pins("4"), Misc("PULL_MODE=UP")),
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# Serial
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("serial", 0,
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Subsignal("rx", Pins("18"), Misc("PULL_MODE=UP")),
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Subsignal("tx", Pins("17"), Misc("PULL_MODE=UP DRIVE=8")),
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IOStandard("LVCMOS33")
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),
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# SPIFlash
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("spiflash", 0,
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Subsignal("cs_n", Pins("60"), Misc("PULL_MODE=UP DRIVE=8")),
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Subsignal("clk", Pins("59"), Misc("PULL_MODE=UP DRIVE=8")),
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Subsignal("miso", Pins("62"), Misc("PULL_MODE=UP")),
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Subsignal("mosi", Pins("61"), Misc("PULL_MODE=UP DRIVE=8")),
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IOStandard("LVCMOS33"),
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),
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# PSRAM
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("O_psram_ck", 0, Pins(2)),
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("O_psram_ck_n", 0, Pins(2)),
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("O_psram_cs_n", 0, Pins(2)),
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("O_psram_reset_n", 0, Pins(2)),
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("IO_psram_dq", 0, Pins(16)),
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("IO_psram_rwds", 0, Pins(2)),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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["J5", "25 26 27 28 29 30 33 34 35 36 37 38 39 40 41 42"],
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["J6", "77 76 75 74 73 72 71 70 69 68 57 56 55 54 53 51"],
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(GowinPlatform):
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default_clk_name = "clk27"
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default_clk_period = 1e9/27e6
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def __init__(self, toolchain="gowin"):
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GowinPlatform.__init__(self, "GW1NR-LV9QN88PC7/I6", _io, _connectors, toolchain=toolchain, devicename="GW1NR-9C")
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self.toolchain.options["use_mspi_as_gpio"] = 1
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self.toolchain.options["use_sspi_as_gpio"] = 1
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def create_programmer(self):
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return OpenFPGALoader("brs-100-gw1nr9")
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def do_finalize(self, fragment):
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GowinPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk27", loose=True), 1e9/27e6)

‎litex_boards/targets/brisbaneSilicon_brs_100_gw1nr9.py‎

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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2026 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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from migen import *
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from litex.gen import *
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from litex_boards.platforms import brisbaneSilicon_brs_100_gw1nr9
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from litex.soc.cores.clock.gowin_gw1n import GW1NPLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.hyperbus import HyperRAM
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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# # #
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# Clk / Rst
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clk27 = platform.request("clk27")
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rst_n = platform.request("user_btn_n", 0)
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# PLL
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self.pll = pll = GW1NPLL(devicename=platform.devicename, device=platform.device)
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self.comb += pll.reset.eq(~rst_n)
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pll.register_clkin(clk27, 27e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, toolchain="gowin", sys_clk_freq=27e6, bios_flash_offset=0x0,
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with_led_chaser = True,
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**kwargs):
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platform = brisbaneSilicon_brs_100_gw1nr9.Platform(toolchain=toolchain)
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq)
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# SoCCore ----------------------------------------------------------------------------------
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# Disable Integrated ROM.
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kwargs["integrated_rom_size"] = 0
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on BrisbaneSilicon BRS-100-GW1NR9", **kwargs)
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# SPI Flash --------------------------------------------------------------------------------
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from litespi.modules import P25Q32H
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="1x", module=P25Q32H(Codes.READ_1_1_1), with_master=False)
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# Add ROM linker region --------------------------------------------------------------------
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self.bus.add_region("rom", SoCRegion(
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origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
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size = 64 * KILOBYTE,
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linker = True)
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)
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self.cpu.set_reset_address(self.bus.regions["rom"].origin)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led_n"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=brisbaneSilicon_brs_100_gw1nr9.Platform, description="LiteX SoC on BrisbaneSilicon BRS-100-GW1NR9.")
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parser.add_target_argument("--flash", action="store_true", help="Flash bitstream and BIOS.")
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parser.add_target_argument("--sys-clk-freq", default=27e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--bios-flash-offset", default="0x0", help="BIOS offset in SPI Flash.")
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args = parser.parse_args()
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soc = BaseSoC(
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toolchain = args.toolchain,
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sys_clk_freq = args.sys_clk_freq,
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bios_flash_offset = int(args.bios_flash_offset, 0),
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**parser.soc_argdict
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)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if args.flash:
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prog = soc.platform.create_programmer()
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prog.flash(0, builder.get_bitstream_filename(mode="flash", ext=".fs"))
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prog.flash(int(args.bios_flash_offset, 0), builder.get_bios_filename(), external=True)
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if __name__ == "__main__":
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main()

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