targets: use exact SDRAM module definitions

Switch targets that already documented their real DRAM devices away from compatible placeholder definitions. This uses the new LiteDRAM module entries for EM638325, W9864G6JT, HY57V641620FTP, H5TQ4G63CFR, and H5TQ4G63EFR.

Author: enjoy-digital

litex_boards/targets/colorlight_i5.py

@@ -22,7 +22,7 @@
 
 from litex.soc.interconnect.csr import *
 
-from litedram.modules import M12L64322A # Compatible with EM638325-6H.
+from litedram.modules import EM638325
 from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
 
 from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
@@ -145,7 +145,7 @@ def __init__(self, board="i5", revision="7.0", toolchain="trellis", sys_clk_freq
             self.sdrphy = sdrphy_cls(platform.request("sdram"))
             self.add_sdram("sdram",
                 phy           = self.sdrphy,
-                module        = M12L64322A(sys_clk_freq, sdram_rate),
+                module        = EM638325(sys_clk_freq, sdram_rate),
                 l2_cache_size = kwargs.get("l2_size", 8192)
             )
 

litex_boards/targets/decklink_quad_hdmi_recorder.py

@@ -26,7 +26,7 @@
 from litex.soc.integration.builder import *
 
 from litedram.common import PHYPadsReducer
-from litedram.modules import MT41J256M16
+from litedram.modules import H5TQ4G63CFR
 from litedram.phy import usddrphy
 
 from litepcie.phy.uspciephy import USPCIEPHY
@@ -83,7 +83,7 @@ def __init__(self, sys_clk_freq=200e6, with_pcie=False, pcie_lanes=4, **kwargs):
                 iodelay_clk_freq = 200e6)
             self.add_sdram("sdram",
                 phy           = self.ddrphy,
-                module        = MT41J256M16(sys_clk_freq, "1:4"),
+                module        = H5TQ4G63CFR(sys_clk_freq, "1:4"),
                 l2_cache_size = kwargs.get("l2_size", 8192)
             )
 

litex_boards/targets/rz_easyfpga.py

@@ -19,7 +19,7 @@
 from litex.soc.integration.builder import *
 from litex.soc.cores.led import LedChaser
 
-from litedram.modules import MT48LC4M16
+from litedram.modules import HY57V641620FTP
 from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
 
 # CRG ----------------------------------------------------------------------------------------------
@@ -77,7 +77,7 @@ def __init__(self, sys_clk_freq=50e6, with_led_chaser=True, sdram_rate="1:1", **
             self.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
             self.add_sdram("sdram",
                 phy           = self.sdrphy,
-                module        = MT48LC4M16(sys_clk_freq, sdram_rate), # Hynix HY57V641620FTP-7
+                module        = HY57V641620FTP(sys_clk_freq, sdram_rate),
                 l2_cache_size = 0
             )
 

litex_boards/targets/sipeed_tang_mega_138k_pro.py

@@ -23,7 +23,7 @@
 
 from litepcie.phy.gw5apciephy import GW5APCIEPHY
 
-from litedram.modules import AS4C32M16, MT41J256M16, W9825G6KH6
+from litedram.modules import AS4C32M16, H5TQ4G63EFR, W9825G6KH6
 from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
 from litedram.phy import GW5DDRPHY
 from litex.build.io import DDROutput
@@ -174,7 +174,7 @@ def __init__(self, sys_clk_freq=50e6,
             self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
             self.add_sdram("sdram",
                 phy           = self.ddrphy,
-                module        = MT41J256M16(sys_clk_freq, "1:2"),
+                module        = H5TQ4G63EFR(sys_clk_freq, "1:2"),
                 l2_cache_size = 0#kwargs.get("l2_size", 8192)
             )
 

litex_boards/targets/trenz_cyc1000.py

@@ -17,7 +17,7 @@
 from litex.soc.integration.builder import *
 from litex.soc.cores.led import LedChaser
 
-from litedram.modules import M12L64322A
+from litedram.modules import W9864G6JT
 from litedram.phy import GENSDRPHY
 
 # CRG ----------------------------------------------------------------------------------------------
@@ -60,7 +60,7 @@ def __init__(self, sys_clk_freq=50e6, with_led_chaser=True, **kwargs):
             self.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
             self.add_sdram("sdram",
                 phy           = self.sdrphy,
-                module        = M12L64322A(sys_clk_freq, "1:1"), # Winbond W9864G6JT
+                module        = W9864G6JT(sys_clk_freq, "1:1"),
                 l2_cache_size = kwargs.get("l2_size", 8192)
             )
 

litex_boards/targets/trenz_max1000.py

@@ -17,7 +17,7 @@
 from litex.soc.integration.builder import *
 from litex.soc.cores.led import LedChaser
 
-from litedram.modules import M12L64322A
+from litedram.modules import W9864G6JT
 from litedram.phy import GENSDRPHY
 
 # CRG ----------------------------------------------------------------------------------------------
@@ -62,7 +62,7 @@ def __init__(self, sys_clk_freq=50e6, with_led_chaser=True, **kwargs):
             self.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
             self.add_sdram("sdram",
                 phy           = self.sdrphy,
-                module        = M12L64322A(sys_clk_freq, "1:1"), # Winbond W9864G6JT
+                module        = W9864G6JT(sys_clk_freq, "1:1"),
                 l2_cache_size = kwargs.get("l2_size", 0)
             )