platforms: Fix TE0025 HyperRAM clock IO standard

Radiant rejects the HyperRAM clk_n pin when the CK/CK# pair is constrained as LVDS, since P6 is not a valid differential negative pin on the LFD2NX-40 CABGA196 package.

The HyperRAM PHY drives clk_p and clk_n as complementary single-ended outputs, matching the rest of the 1.8 V HyperRAM bus, so constrain both clock pins as LVCMOS18H.

Verified with: python3 trenz_tel0025.py --build --output-dir /tmp/litex-trenz_tel0025-radiant-fixed --build-log

Author: enjoy-digital

litex_boards/platforms/trenz_tel0025.py

@@ -75,8 +75,8 @@
         Subsignal("rwds",  Pins("N5"),                      IOStandard("LVCMOS18H")),
         Subsignal("cs_n",  Pins("K4"),                      IOStandard("LVCMOS18H")),
         Subsignal("rst_n", Pins("L4"),                      IOStandard("LVCMOS18H")),
-        Subsignal("clk_p", Pins("N6"),                      IOStandard("LVDS")),
-        Subsignal("clk_n", Pins("P6"),                      IOStandard("LVDS")),
+        Subsignal("clk_p", Pins("N6"),                      IOStandard("LVCMOS18H")),
+        Subsignal("clk_n", Pins("P6"),                      IOStandard("LVCMOS18H")),
         Misc("SLEWRATE=FAST"),
     ),