targets/adiuvo_forgix: add RP2350 SPIBone option

Add --with-spibone to expose a 3-wire SPIBone Wishbone master on the RP2350 passive-SPI pins. This provides an optional post-configuration RP2350 control path while leaving UARTBone as the default target interface.

Use 3-wire mode because the published RP2350 loader configuration has no dedicated FPGA MISO pin, so MOSI is reused bidirectionally by SPIBone.

References:

- https://bitbucket.org/adiuvo-engineering/forgix_public/src/main/Schematic/RP2350_FPGA_eensy.pdf

- https://bitbucket.org/adiuvo-engineering/forgix_public/src/main/Kicad_Project/RP2350_FPGA_eensy-main.zip

- https://github.com/enjoy-digital/litex_rp2040_pmod_test

Author: enjoy-digital

litex_boards/platforms/adiuvo_forgix.py

@@ -36,6 +36,14 @@
         IOStandard("3.3_V_LVTTL_/_LVCMOS"),
     ),
 
+    # Optional 3-wire SPIBone over the RP2350 passive-SPI pins.
+    ("spibone", 0,
+        Subsignal("cs_n", Pins("G3")),
+        Subsignal("clk",  Pins("F3")),
+        Subsignal("mosi", Pins("F2")),
+        IOStandard("3.3_V_LVTTL_/_LVCMOS"),
+    ),
+
     # FPGA I/Os routed to the Teensy-style edge connector.
     ("user_io", 0, Pins(
         "A5 D7 C7 D6 G7 G5 G2 F5 F6",

litex_boards/targets/adiuvo_forgix.py

@@ -15,6 +15,7 @@
 from litex.soc.integration.soc import *
 from litex.soc.integration.builder import *
 from litex.soc.cores.led import LedChaser
+from litex.soc.cores.spi.spi_bone import SPIBone
 
 # CRG ----------------------------------------------------------------------------------------------
 
@@ -37,7 +38,7 @@ def __init__(self, platform, sys_clk_freq):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCMini):
-    def __init__(self, sys_clk_freq=32e6, with_led_chaser=True, **kwargs):
+    def __init__(self, sys_clk_freq=32e6, with_spibone=False, with_led_chaser=True, **kwargs):
         platform = adiuvo_forgix.Platform()
 
         # CRG --------------------------------------------------------------------------------------
@@ -53,6 +54,12 @@ def __init__(self, sys_clk_freq=32e6, with_led_chaser=True, **kwargs):
         kwargs["with_uartbone"]        = True
         SoCMini.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Adiuvo Forgix", **kwargs)
 
+        # RP2350 <-> MMAP over 3-wire SPIBone. See the RP-side USB/SPI bridge approach:
+        # https://github.com/enjoy-digital/litex_rp2040_pmod_test
+        if with_spibone:
+            self.spibone = SPIBone(platform.request("spibone"), wires=3)
+            self.bus.add_master(name="spibone", master=self.spibone.bus)
+
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser:
             self.leds = LedChaser(
@@ -66,6 +73,7 @@ def main():
     from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=adiuvo_forgix.Platform, description="LiteX SoC on Adiuvo Forgix.")
     parser.add_target_argument("--sys-clk-freq", default=32e6, type=float, help="System clock frequency.")
+    parser.add_target_argument("--with-spibone", action="store_true", help="Add SPIBone on the RP2350 SPI pins.")
     parser.set_defaults(
         cpu_type             = "None",
         integrated_sram_size = 0,
@@ -77,6 +85,7 @@ def main():
 
     soc = BaseSoC(
         sys_clk_freq = args.sys_clk_freq,
+        with_spibone = args.with_spibone,
         **parser.soc_argdict)
     builder = Builder(soc, **parser.builder_argdict)
     if args.build: