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gatecatgatecat
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genesys2: Add HDMI output
Signed-off-by: gatecat <gatecat@ds0.me>
1 parent 30dc7d2 commit 9194643

2 files changed

Lines changed: 70 additions & 19 deletions

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‎litex_boards/platforms/digilent_genesys2.py‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -135,6 +135,22 @@
135135
Subsignal("tx_ctl", Pins(" AK14"), IOStandard("LVCMOS15")),
136136
Subsignal("tx_data", Pins("AJ12 AK11 AJ11 AK10"), IOStandard("LVCMOS15")),
137137
),
138+
139+
# HDMI Out
140+
("hdmi_out", 0,
141+
Subsignal("clk_p", Pins("AA20"), IOStandard("TMDS_33")),
142+
Subsignal("clk_n", Pins("AB20"), IOStandard("TMDS_33")),
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Subsignal("data0_p", Pins("AC20"), IOStandard("TMDS_33")),
144+
Subsignal("data0_n", Pins("AC21"), IOStandard("TMDS_33")),
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Subsignal("data1_p", Pins("AA22"), IOStandard("TMDS_33")),
146+
Subsignal("data1_n", Pins("AA23"), IOStandard("TMDS_33")),
147+
Subsignal("data2_p", Pins("AB24"), IOStandard("TMDS_33")),
148+
Subsignal("data2_n", Pins("AC25"), IOStandard("TMDS_33")),
149+
Subsignal("scl", Pins("AF27"), IOStandard("LVCMOS33")),
150+
Subsignal("sda", Pins("AF26"), IOStandard("LVCMOS33")),
151+
Subsignal("cec", Pins("Y24"), IOStandard("LVCMOS33")),
152+
Subsignal("hdp", Pins("AG29"), IOStandard("LVCMOS33")),
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),
138154
]
139155

140156
# Connectors ---------------------------------------------------------------------------------------

‎litex_boards/targets/digilent_genesys2.py‎

Lines changed: 54 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -12,10 +12,12 @@
1212

1313
from litex_boards.platforms import digilent_genesys2
1414

15+
from litex.build.io import DifferentialInput
1516
from litex.soc.cores.clock import *
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from litex.soc.integration.soc import SoCRegion
1718
from litex.soc.integration.soc_core import *
1819
from litex.soc.integration.builder import *
20+
from litex.soc.cores.video import VideoS7HDMIPHY
1921
from litex.soc.cores.led import LedChaser
2022

2123
from litedram.modules import MT41J256M16
@@ -26,40 +28,60 @@
2628
# CRG ----------------------------------------------------------------------------------------------
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2830
class _CRG(LiteXModule):
29-
def __init__(self, platform, sys_clk_freq):
31+
def __init__(self, platform, sys_clk_freq, with_video_pll=False):
3032
self.rst = Signal()
3133
self.cd_sys = ClockDomain()
3234
self.cd_sys4x = ClockDomain()
3335
self.cd_idelay = ClockDomain()
3436

37+
self.cd_hdmi = ClockDomain()
38+
self.cd_hdmi5x = ClockDomain()
39+
3540
# # #
3641

42+
clk200_pad = platform.request("clk200")
43+
rst_n = platform.request("cpu_reset_n")
44+
clk200 = Signal()
45+
46+
self.specials += DifferentialInput(clk200_pad.p, clk200_pad.n, clk200)
47+
3748
self.pll = pll = S7MMCM(speedgrade=-2)
38-
self.comb += pll.reset.eq(~platform.request("cpu_reset_n") | self.rst)
39-
pll.register_clkin(platform.request("clk200"), 200e6)
49+
self.comb += pll.reset.eq(~rst_n | self.rst)
50+
pll.register_clkin(clk200, 200e6)
4051
pll.create_clkout(self.cd_sys, sys_clk_freq)
4152
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
4253
pll.create_clkout(self.cd_idelay, 200e6)
4354
platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
4455

4556
self.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
4657

58+
# Video PLL.
59+
if with_video_pll:
60+
self.video_pll = video_pll = S7MMCM(speedgrade=-2)
61+
video_pll.reset.eq(~rst_n | self.rst)
62+
video_pll.register_clkin(clk200, 200e6)
63+
video_pll.create_clkout(self.cd_hdmi, 40e6)
64+
video_pll.create_clkout(self.cd_hdmi5x, 5*40e6)
65+
66+
4767
# BaseSoC ------------------------------------------------------------------------------------------
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4969
class BaseSoC(SoCCore):
5070
def __init__(self, sys_clk_freq=100e6, toolchain="vivado",
51-
with_ethernet = False,
52-
with_etherbone = False,
53-
eth_ip = "192.168.1.50",
54-
remote_ip = None,
55-
eth_dynamic_ip = False,
56-
with_led_chaser = True,
57-
with_can = False,
71+
with_ethernet = False,
72+
with_etherbone = False,
73+
eth_ip = "192.168.1.50",
74+
remote_ip = None,
75+
eth_dynamic_ip = False,
76+
with_led_chaser = True,
77+
with_can = False,
78+
with_video_terminal = False,
79+
with_video_framebuffer = False,
5880
**kwargs):
5981
platform = digilent_genesys2.Platform(toolchain=toolchain)
6082

6183
# CRG --------------------------------------------------------------------------------------
62-
self.crg = _CRG(platform, sys_clk_freq)
84+
self.crg = _CRG(platform, sys_clk_freq, with_video_terminal or with_video_framebuffer)
6385

6486
# SoCCore ----------------------------------------------------------------------------------
6587
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Genesys2", **kwargs)
@@ -86,6 +108,14 @@ def __init__(self, sys_clk_freq=100e6, toolchain="vivado",
86108
if with_ethernet:
87109
self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip, local_ip=eth_ip, remote_ip=remote_ip)
88110

111+
# Video ------------------------------------------------------------------------------------
112+
if with_video_terminal or with_video_framebuffer:
113+
self.videophy = VideoS7HDMIPHY(platform.request("hdmi_out"), clock_domain="hdmi")
114+
if with_video_terminal:
115+
self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
116+
if with_video_framebuffer:
117+
self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
118+
89119
# Leds -------------------------------------------------------------------------------------
90120
if with_led_chaser:
91121
self.leds = LedChaser(
@@ -117,17 +147,22 @@ def main():
117147
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
118148
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
119149
parser.add_target_argument("--with-can", action="store_true", help="Enable CAN support (Through CTU-CAN-FD Core and SN65HVD230 'PMOD'.")
150+
viopts = parser.target_group.add_mutually_exclusive_group()
151+
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
152+
viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
120153
args = parser.parse_args()
121154

122155
soc = BaseSoC(
123-
sys_clk_freq = args.sys_clk_freq,
124-
toolchain = args.toolchain,
125-
with_ethernet = args.with_ethernet,
126-
eth_ip = args.eth_ip,
127-
eth_dynamic_ip = args.eth_dynamic_ip,
128-
remote_ip = args.remote_ip,
129-
with_etherbone = args.with_etherbone,
130-
with_can = args.with_can,
156+
sys_clk_freq = args.sys_clk_freq,
157+
toolchain = args.toolchain,
158+
with_ethernet = args.with_ethernet,
159+
eth_ip = args.eth_ip,
160+
eth_dynamic_ip = args.eth_dynamic_ip,
161+
remote_ip = args.remote_ip,
162+
with_etherbone = args.with_etherbone,
163+
with_can = args.with_can,
164+
with_video_terminal = args.with_video_terminal,
165+
with_video_framebuffer = args.with_video_framebuffer,
131166
**parser.soc_argdict
132167
)
133168

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