Skip to content

Commit b5f5547

Browse files
enjoy-digitalenjoy-digital
committed
platforms/targets: add Adiuvo Forgix board support
Add a platform and CPU-less LiteX target for the Adiuvo Forgix board based on the Efinix Trion T8F49C2 FPGA. The platform maps the 32 MHz oscillator, RGB LED, RP2350 passive-SPI configuration pins, and Teensy-style edge connector from the shared schematic/KiCad design. The target keeps the default design small with UARTBone and a LED chaser and generates passive x1 Efinity images for the RP2350 loader. List the board in the generated README and board inventory, and mark it as Efinity-gated in the CI target/platform metadata so generic runners skip the external-toolchain build while Efinity-capable runners can still exercise it. References: - https://bitbucket.org/adiuvo-engineering/forgix_public/src/main/Schematic/RP2350_FPGA_eensy.pdf - https://bitbucket.org/adiuvo-engineering/forgix_public/src/main/Kicad_Project/RP2350_FPGA_eensy-main.zip - https://bitbucket.org/adiuvo-engineering/forgix_public/src/main/BitStream_Loader/README.md
1 parent 12f023f commit b5f5547

5 files changed

Lines changed: 181 additions & 0 deletions

File tree

‎README.md‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -96,6 +96,7 @@ Some of the supported boards, see yours? Give LiteX-Boards a try!
9696
---------------
9797
├── adi_adrv2crr_fmc
9898
├── adi_plutosdr
99+
├── adiuvo_forgix
99100
├── alchitry_au
100101
├── alchitry_au_v2
101102
├── alchitry_cu

‎docs/boards_inventory.md‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@ python3 .github/scripts/generate_board_inventory.py --write
1010
| --- | --- | --- | --- | --- | --- |
1111
| `adi_adrv2crr_fmc` | adi_adrv2crr_fmc | - | `150000000.0` | PCIe | included |
1212
| `adi_plutosdr` | adi_plutosdr | vivado | `100000000.0` | - | included |
13+
| `adiuvo_forgix` | adiuvo_forgix | efinity | `32000000.0` | - | toolchain-gated: Require Efinity toolchain. |
1314
| `alchitry_au` | alchitry_au | vivado | `83333000.0` | SPI Flash | included |
1415
| `alchitry_au_v2` | alchitry_au_v2 | vivado | `100000000.0` | SPI Flash | included |
1516
| `alchitry_cu` | alchitry_cu | icestorm | `50000000.0` | - | included |

‎litex_boards/platforms/adiuvo_forgix.py‎

Lines changed: 85 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,85 @@
1+
#
2+
# This file is part of LiteX-Boards.
3+
#
4+
# Copyright (c) 2026 Florent Kermarrec <florent@enjoy-digital.fr>
5+
# SPDX-License-Identifier: BSD-2-Clause
6+
7+
from litex.build.generic_platform import *
8+
from litex.build.efinix.platform import EfinixPlatform
9+
10+
# IOs ----------------------------------------------------------------------------------------------
11+
12+
_io = [
13+
# Clk.
14+
("clk32", 0, Pins("B4"), IOStandard("3.3_V_LVTTL_/_LVCMOS")),
15+
16+
# Leds.
17+
("user_led_n", 0, Pins("E1"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=1")), # Red.
18+
("user_led_n", 1, Pins("F1"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=1")), # Green.
19+
("user_led_n", 2, Pins("G1"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=1")), # Blue.
20+
21+
# Serial on FPGA header pins 4/5.
22+
("serial", 0,
23+
Subsignal("rx", Pins("A5")),
24+
Subsignal("tx", Pins("D7")),
25+
IOStandard("3.3_V_LVTTL_/_LVCMOS"),
26+
),
27+
28+
# RP2350 passive-SPI configuration interface.
29+
("fpga_cfg", 0,
30+
Subsignal("cs_n", Pins("G3")),
31+
Subsignal("clk", Pins("F3")),
32+
Subsignal("mosi", Pins("F2")),
33+
Subsignal("reset_n", Pins("G4")),
34+
Subsignal("done", Pins("F4")),
35+
Subsignal("status_n", Pins("A4")),
36+
IOStandard("3.3_V_LVTTL_/_LVCMOS"),
37+
),
38+
39+
# FPGA I/Os routed to the Teensy-style edge connector.
40+
("user_io", 0, Pins(
41+
"A5 D7 C7 D6 G7 G5 G2 F5 F6",
42+
"E5 C6 B3 B7 A7 A3 C2 D2 E2"),
43+
IOStandard("3.3_V_LVTTL_/_LVCMOS"),
44+
),
45+
]
46+
47+
# Bank voltage -------------------------------------------------------------------------------------
48+
49+
_bank_info = [
50+
("1A", "3.3 V LVTTL / LVCMOS"),
51+
("1B", "3.3 V LVTTL / LVCMOS"),
52+
("1C", "1.1 V"),
53+
("2A", "3.3 V LVTTL / LVCMOS"),
54+
("2B", "3.3 V LVTTL / LVCMOS"),
55+
]
56+
57+
# Connectors ---------------------------------------------------------------------------------------
58+
59+
_connectors = [
60+
# Teensy-style edge connector. Use "teensy:1" for connector pin 1.
61+
("teensy",
62+
"ZERO "
63+
"#N/A #N/A #N/A #N/A #N/A A5 D7 C7 #N/A #N/A D6 G7 G5 G2 #N/A #N/A #N/A #N/A #N/A "
64+
"F5 F6 E5 C6 B3 B7 A7 A3 C2 D2 E2 #N/A #N/A #N/A"
65+
),
66+
]
67+
68+
# Platform -----------------------------------------------------------------------------------------
69+
70+
class Platform(EfinixPlatform):
71+
default_clk_name = "clk32"
72+
default_clk_freq = 32e6
73+
default_clk_period = 1e9/32e6
74+
75+
def __init__(self, toolchain="efinity"):
76+
EfinixPlatform.__init__(self,
77+
"T8F49C2", _io, _connectors,
78+
iobank_info = _bank_info,
79+
toolchain = toolchain,
80+
spi_mode = "passive",
81+
spi_width = "1")
82+
83+
def do_finalize(self, fragment):
84+
EfinixPlatform.do_finalize(self, fragment)
85+
self.add_period_constraint(self.lookup_request("clk32", loose=True), 1e9/32e6)

‎litex_boards/targets/adiuvo_forgix.py‎

Lines changed: 86 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,86 @@
1+
#!/usr/bin/env python3
2+
3+
#
4+
# This file is part of LiteX-Boards.
5+
#
6+
# Copyright (c) 2026 Florent Kermarrec <florent@enjoy-digital.fr>
7+
# SPDX-License-Identifier: BSD-2-Clause
8+
9+
from migen import *
10+
11+
from litex.gen import *
12+
13+
from litex_boards.platforms import adiuvo_forgix
14+
15+
from litex.soc.integration.soc import *
16+
from litex.soc.integration.builder import *
17+
from litex.soc.cores.led import LedChaser
18+
19+
# CRG ----------------------------------------------------------------------------------------------
20+
21+
class _CRG(LiteXModule):
22+
def __init__(self, platform, sys_clk_freq):
23+
assert sys_clk_freq == platform.default_clk_freq
24+
25+
self.rst = Signal()
26+
self.cd_sys = ClockDomain()
27+
28+
# # #
29+
30+
clk32 = platform.request("clk32")
31+
32+
self.comb += [
33+
self.cd_sys.clk.eq(clk32),
34+
self.cd_sys.rst.eq(self.rst),
35+
]
36+
37+
# BaseSoC ------------------------------------------------------------------------------------------
38+
39+
class BaseSoC(SoCMini):
40+
def __init__(self, sys_clk_freq=32e6, with_led_chaser=True, **kwargs):
41+
platform = adiuvo_forgix.Platform()
42+
43+
# CRG --------------------------------------------------------------------------------------
44+
self.crg = _CRG(platform, sys_clk_freq)
45+
46+
# SoCMini ----------------------------------------------------------------------------------
47+
kwargs["cpu_type"] = "None"
48+
kwargs["integrated_sram_size"] = 0
49+
kwargs["integrated_rom_size"] = 0
50+
kwargs["with_uart"] = False
51+
kwargs["with_timer"] = False
52+
kwargs["uart_name"] = "crossover"
53+
kwargs["with_uartbone"] = True
54+
SoCMini.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Adiuvo Forgix", **kwargs)
55+
56+
# Leds -------------------------------------------------------------------------------------
57+
if with_led_chaser:
58+
self.leds = LedChaser(
59+
pads = platform.request_all("user_led_n"),
60+
sys_clk_freq = sys_clk_freq,
61+
polarity = 1)
62+
63+
# Build --------------------------------------------------------------------------------------------
64+
65+
def main():
66+
from litex.build.parser import LiteXArgumentParser
67+
parser = LiteXArgumentParser(platform=adiuvo_forgix.Platform, description="LiteX SoC on Adiuvo Forgix.")
68+
parser.add_target_argument("--sys-clk-freq", default=32e6, type=float, help="System clock frequency.")
69+
parser.set_defaults(
70+
cpu_type = "None",
71+
integrated_sram_size = 0,
72+
no_uart = True,
73+
no_timer = True,
74+
uart_name = "crossover",
75+
with_uartbone = True)
76+
args = parser.parse_args()
77+
78+
soc = BaseSoC(
79+
sys_clk_freq = args.sys_clk_freq,
80+
**parser.soc_argdict)
81+
builder = Builder(soc, **parser.builder_argdict)
82+
if args.build:
83+
builder.build(**parser.toolchain_argdict)
84+
85+
if __name__ == "__main__":
86+
main()

‎test/test_targets.py‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -78,6 +78,10 @@
7878
"category": "external_toolchain",
7979
"reason": "Require Efinity toolchain.",
8080
},
81+
"adiuvo_forgix": {
82+
"category": "external_toolchain",
83+
"reason": "Require Efinity toolchain.",
84+
},
8185
"adi_plutosdr": {
8286
"category": "missing_default_clock",
8387
"reason": "No default clock.",
@@ -153,6 +157,10 @@
153157
"category": "external_toolchain",
154158
"reason": "Require Efinity toolchain.",
155159
},
160+
"adiuvo_forgix": {
161+
"category": "external_toolchain",
162+
"reason": "Require Efinity toolchain.",
163+
},
156164
}
157165

158166

0 commit comments

Comments
 (0)