Merge pull request #676 from michael-betz/marble_vcxo_en

berkeleylab_marble: add missing enable pin for 20 MHz VCXO

Author: enjoy-digital

litex_boards/platforms/berkeleylab_marble.py

@@ -37,27 +37,28 @@
     ),
     # Tunable VCXO. Warning: Non clock-capable pin
     ("clk20", 0, Pins("W11"), IOStandard("LVCMOS15")),
+    ("clk20_en", 0, Pins("V9"), IOStandard("LVCMOS15"), Misc("PULLUP=TRUE")),
     # Main system clock. White rabbit compatible
     ("clk125", 0,
         Subsignal("p", Pins("AC9"), IOStandard("DIFF_SSTL15")),
         Subsignal("n", Pins("AD9"), IOStandard("DIFF_SSTL15")),
     ),
     # 4x Multi gigabit clocks from cross-point switch, source configured by MMC
     ("clkmgt", 0,
-        Subsignal("p", Pins("D6"), IOStandard("DIFF_SSTL15")),
-        Subsignal("n", Pins("D5"), IOStandard("DIFF_SSTL15")),
+        Subsignal("p", Pins("D6")),
+        Subsignal("n", Pins("D5")),
     ),
     ("clkmgt", 1,
-        Subsignal("p", Pins("F6"), IOStandard("DIFF_SSTL15")),
-        Subsignal("n", Pins("F5"), IOStandard("DIFF_SSTL15")),
+        Subsignal("p", Pins("F6")),
+        Subsignal("n", Pins("F5")),
     ),
     ("clkmgt", 2,
-        Subsignal("p", Pins("H6"), IOStandard("DIFF_SSTL15")),
-        Subsignal("n", Pins("H5"), IOStandard("DIFF_SSTL15")),
+        Subsignal("p", Pins("H6")),
+        Subsignal("n", Pins("H5")),
     ),
     ("clkmgt", 3,
-        Subsignal("p", Pins("K6"), IOStandard("DIFF_SSTL15")),
-        Subsignal("n", Pins("K5"), IOStandard("DIFF_SSTL15")),
+        Subsignal("p", Pins("K6")),
+        Subsignal("n", Pins("K5")),
     ),
     # 2x LED: LD16 and LD17
     ("user_led", 0, Pins("Y13"), IOStandard("LVCMOS15")),

litex_boards/targets/berkeleylab_marble.py

@@ -74,6 +74,7 @@ def __init__(self, sys_clk_freq=125e6,
         with_etherbone  = False,
         with_rts_reset  = False,
         with_led_chaser = True,
+        with_i2c        = True,
         spd_dump        = None,
         **kwargs):
         platform = berkeleylab_marble.Platform()
@@ -131,9 +132,10 @@ def __init__(self, sys_clk_freq=125e6,
         if with_etherbone:
             self.add_etherbone(phy=self.ethphy, buffer_depth=255)
 
-        # System I2C (behing multiplexer) ----------------------------------------------------------
-        i2c_pads = platform.request('i2c_fpga')
-        self.i2c = I2CMaster(i2c_pads)
+        # System I2C (behind multiplexer) ----------------------------------------------------------
+        if with_i2c:
+            i2c_pads = platform.request('i2c_fpga')
+            self.i2c = I2CMaster(i2c_pads)
 
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser: