Merge pull request #770 from litex-hub/efinix-ti60-hyperram-integration

targets/efinix_ti60: use common HyperRAM integration

Author: enjoy-digital

litex_boards/targets/efinix_ti60_f225_dev_kit.py

@@ -16,10 +16,6 @@
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc import *
 from litex.soc.integration.builder import *
-from litex.soc.integration.soc import SoCRegion
-from litex.soc.interconnect import wishbone
-
-from litex.soc.cores.hyperbus import HyperRAM
 
 from liteeth.phy.titaniumrgmii import LiteEthPHYRGMII
 
@@ -87,35 +83,16 @@ def __init__(self, sys_clk_freq=200e6,
 
         # HyperRAM ---------------------------------------------------------------------------------
         if with_hyperram:
-            # HyperRAM Parameters.
-            hyperram_device     = "W958D6NW"
-            hyperram_size       = 32 * MEGABYTE
-            hyperram_cache_size = 16 * KILOBYTE
-
-            # HyperRAM Bus/Slave Interface.
-            hyperram_bus = wishbone.Interface(data_width=32, address_width=32, addressing="word")
-            self.bus.add_slave(name="main_ram", slave=hyperram_bus, region=SoCRegion(origin=0x40000000, size=hyperram_size, mode="rwx"))
-
-            # HyperRAM L2 Cache.
-            hyperram_cache = wishbone.Cache(
-                cachesize = hyperram_cache_size//4,
-                master    = hyperram_bus,
-                slave     = wishbone.Interface(data_width=32, address_width=32, addressing="word")
-            )
-            hyperram_cache = FullMemoryWE()(hyperram_cache)
-            self.hyperram_cache = hyperram_cache
-            self.add_config("L2_SIZE", hyperram_cache_size)
-
-            # HyperRAM Core.
-            self.hyperram = HyperRAM(
-                pads         = platform.request("hyperram"),
-                latency      = 7,
-                latency_mode = "variable",
-                sys_clk_freq = sys_clk_freq,
-                clk_ratio    = "2:1",
-                dq_i_cd      = "sys2x_ps",
+            self.add_hyperram(
+                region_name   = "main_ram",
+                origin        = self.mem_map["main_ram"],
+                size          = 32*MEGABYTE,
+                l2_cache_size = 16*KILOBYTE,
+                latency       = 7,
+                latency_mode  = "variable",
+                clk_ratio     = "2:1",
+                dq_i_cd       = "sys2x_ps",
             )
-            self.comb += self.hyperram_cache.slave.connect(self.hyperram.bus)
 
         # Ethernet / Etherbone ---------------------------------------------------------------------
         if with_ethernet or with_etherbone: