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add QMTech Cyclone10 Starter Kit support - 10CL080 - #683

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trabucayre merged 2 commits into
litex-hub:masterfrom
0xDRRB:master
Jul 26, 2025
Merged

add QMTech Cyclone10 Starter Kit support - 10CL080#683
trabucayre merged 2 commits into
litex-hub:masterfrom
0xDRRB:master

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@0xDRRB

@0xDRRB 0xDRRB commented Jul 24, 2025

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Hi,

Basic support for this one : https://fr.aliexpress.com/item/1005006846173314.html

The RTL8211EG RGMII/GMII Ethernet PHY does not appear to be supported by LiteEth on Altera, so there is no Ethernet :(

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2025 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Jul 24 2025 15:41:53
 BIOS CRC passed (4625eba0)

 LiteX git sha1: eda4e49b7

--=============== SoC ==================--
CPU:            VexRiscv @ 50MHz
BUS:            wishbone 32-bit @ 4GiB
CSR:            32-bit data
ROM:            128.0KiB
SRAM:           8.0KiB
L2:             8.0KiB
SDRAM:          32.0MiB 16-bit @ 100MT/s (CL-2 CWL-2)
MAIN-RAM:       32.0MiB

--========== Initialization ============--

Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
  Write: 0x40000000-0x40200000 2.0MiB     
   Read: 0x40000000-0x40200000 2.0MiB     
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
  Write speed: 17.4MiB/s
   Read speed: 26.0MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
Booting from SDCard in SPI-Mode...
Booting from boot.json...
Booting from boot.bin...
SDCard boot failed.
No boot medium found

--============= Console ================--

litex> 

This is largely based on the work of Hans Baier for qmtech_10cl006.

Comment on lines +19 to +24
("user_led", 0, Pins("V10"), IOStandard("3.3-V LVTTL")), # D1
("user_led", 1, Pins("U9"), IOStandard("3.3-V LVTTL")), # D2
("user_led", 2, Pins("V9"), IOStandard("3.3-V LVTTL")), # D3
("user_led", 3, Pins("V8"), IOStandard("3.3-V LVTTL")), # D4
("user_led", 4, Pins("V5"), IOStandard("3.3-V LVTTL")), # D5
("user_led", 5, Pins("Y4"), IOStandard("3.3-V LVTTL")), # D6

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Please align IOStandard

Comment on lines +28 to +29
Subsignal("dig", Pins("U11 V16 AA18")),
Subsignal("segments", Pins("W14 AB19 AB18 V13 U12 V15 AA19 U14")), # A B C D E F G dot

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ditto

Comment on lines +34 to +35
("key", 0, Pins("P4"), IOStandard("3.3-V LVTTL")),
("key", 1, Pins("P3"), IOStandard("3.3-V LVTTL")),

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One space before IOSTandard


# SPIFlash (W25Q128)
("spiflash", 0,
# clk

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clk or cs_n ? :-)

Comment on lines +68 to +69
with_led_chaser = True,
sdram_rate = "1:1",

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Why a lot of space ?

Comment on lines +114 to +115
sys_clk_freq = args.sys_clk_freq,
sdram_rate = args.sdram_rate,

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Same question: too many space

@trabucayre

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Hi @0xDRRB and thanks!
LGTM just few remarks.
For RGMII support: due to it specificities it requires a dedicated Module. One implementation (for Agilex5) exists here but present a limitation related to delay.

@trabucayre
trabucayre merged commit 54eb65a into litex-hub:master Jul 26, 2025
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@trabucayre

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Applied. Thanks @0xDRRB !

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2 participants