targets/efinix_tz170: use common hard DDR integration

[enjoy-digital]

Summary

• move the board-specific LPDDR4 geometry into the platform
• replace the target-local Efinity DDR generator and bus adapters with the common LiteX integration
• preserve the dedicated 33.33 MHz to 600 MHz DDR controller PLL
• support both native VexiiRiscv AXI and default bus-adapted CPU configurations

This is a follow-up to litex-hub/litex-boards#765
and depends on enjoy-digital/litex#2544.

Validation

• default VexRiscv/Wishbone generation and Efinity Interface Designer checks pass
• VexiiRiscv native-AXI generation and Efinity Interface Designer checks pass
• the old/new Efinity peripheral databases match except for their generation timestamps
• full default VexRiscv Efinity 2025.1 synthesis, place-and-route, timing analysis,
  programming-file generation, and bitstream generation pass
  • 100 MHz system setup slack: +1.827 ns
  • estimated maximum system frequency: 122.354 MHz
• a full four-core VexiiRiscv flow also produces a bitstream, but the existing 175 MHz
  CPU configuration does not meet timing (-0.901 ns, estimated maximum 151.172 MHz)