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targets: uses self.cpu.set_libxil instead of explicit/dupplicated code for all boards based on zynq7000/zynmpMP #772

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Merged
enjoy-digital merged 1 commit into from
Jul 28, 2026
Merged

targets: uses self.cpu.set_libxil instead of explicit/dupplicated code for all boards based on zynq7000/zynmpMP #772

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75 changes: 9 additions & 66 deletions litex_boards/targets/alinx_axu2cga.py
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Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -16,17 +16,12 @@
# Relies on https://github.com/lucaceresoli/zynqmp-pmufw-builder to create a generic PMU firmware;
# first build will take a while because it includes a cross-toolchain.

import os

from migen import *

from litex.gen import *

from litex_boards.platforms import alinx_axu2cga

from litex.build.tools import write_to_file


from litex.soc.cores.clock import *
from litex.soc.integration.soc import *
from litex.soc.integration.soc import SoCRegion
Expand Down Expand Up @@ -89,70 +84,22 @@ def __init__(self, sys_clk_freq=25e6, with_led_chaser=True, **kwargs):
linker = True)
)
self.constants["CONFIG_CLOCK_FREQUENCY"] = 1199880127
self.cpu.set_libxil({
"STDIN_BASEADDRESS" : "0xFF010000",
"STDOUT_BASEADDRESS" : "0xFF010000",
"XPAR_PSU_DDR_0_S_AXI_BASEADDR" : "0x00000000",
"XPAR_PSU_DDR_0_S_AXI_HIGHADDR" : "0x7FFFFFFF",
"XPAR_PSU_DDR_1_S_AXI_BASEADDR" : "0x800000000",
"XPAR_PSU_DDR_1_S_AXI_HIGHADDR" : "0x87FFFFFFF",
"XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ" : "99999005",
})

# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

def finalize(self, *args, **kwargs):
super(BaseSoC, self).finalize(*args, **kwargs)
if self.cpu_type != "zynqmp":
return

libxil_path = os.path.join(self.builder.software_dir, 'libxil')
os.makedirs(os.path.realpath(libxil_path), exist_ok=True)
lib = os.path.join(libxil_path, 'embeddedsw')
if not os.path.exists(lib):
os.system("git clone --depth 1 https://github.com/Xilinx/embeddedsw {}".format(lib))

os.makedirs(os.path.realpath(self.builder.include_dir), exist_ok=True)

for header in [
'XilinxProcessorIPLib/drivers/uartps/src/xuartps_hw.h',
'lib/bsp/standalone/src/common/xil_types.h',
'lib/bsp/standalone/src/common/xil_assert.h',
'lib/bsp/standalone/src/common/xil_io.h',
'lib/bsp/standalone/src/common/xil_printf.h',
'lib/bsp/standalone/src/common/xstatus.h',
'lib/bsp/standalone/src/common/xdebug.h',
'lib/bsp/standalone/src/arm/ARMv8/64bit/xpseudo_asm.h',
'lib/bsp/standalone/src/arm/ARMv8/64bit/xreg_cortexa53.h',
'lib/bsp/standalone/src/arm/ARMv8/64bit/xil_cache.h',
'lib/bsp/standalone/src/arm/ARMv8/64bit/xil_errata.h',
'lib/bsp/standalone/src/arm/ARMv8/64bit/platform/ZynqMP/xparameters_ps.h',
'lib/bsp/standalone/src/arm/common/xil_exception.h',
'lib/bsp/standalone/src/arm/common/gcc/xpseudo_asm_gcc.h',
]:
shutil.copy(os.path.join(lib, header), self.builder.include_dir)

write_to_file(os.path.join(self.builder.include_dir, 'bspconfig.h'), """
#ifndef BSPCONFIG_H
#define BSPCONFIG_H

#define EL3 1
#define EL1_NONSECURE 0

#endif
""")
write_to_file(os.path.join(self.builder.include_dir, 'xparameters.h'), '''
#ifndef XPARAMETERS_H
#define XPARAMETERS_H

#include "xparameters_ps.h"

#define STDIN_BASEADDRESS 0xFF010000
#define STDOUT_BASEADDRESS 0xFF010000
#define XPAR_PSU_DDR_0_S_AXI_BASEADDR 0x00000000
#define XPAR_PSU_DDR_0_S_AXI_HIGHADDR 0x7FFFFFFF
#define XPAR_PSU_DDR_1_S_AXI_BASEADDR 0x800000000
#define XPAR_PSU_DDR_1_S_AXI_HIGHADDR 0x87FFFFFFF
#define XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ 99999005

#endif
''')

# Build --------------------------------------------------------------------------------------------

def main():
Expand All @@ -168,10 +115,6 @@ def main():
**parser.soc_argdict
)
builder = Builder(soc, **parser.builder_argdict)
if args.cpu_type == "zynqmp":
soc.builder = builder
builder.add_software_package('libxil')
builder.add_software_library('libxil')
if args.build:
builder.build(**parser.toolchain_argdict)

Expand Down
56 changes: 5 additions & 51 deletions litex_boards/targets/digilent_arty_z7.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -32,8 +32,6 @@
from litex.gen import *

from litex_boards.platforms import digilent_arty_z7
from litex.build.tools import write_to_file


from litex.soc.cores.clock import *
from litex.soc.integration.soc import *
Expand Down Expand Up @@ -107,58 +105,18 @@ def __init__(self, variant="z7-20", toolchain="vivado", sys_clk_freq=125e6,
)
self.constants["CONFIG_CLOCK_FREQUENCY"] = 666666687
self.bus.add_region("flash", SoCRegion(origin=0xFC00_0000, size=0x4_0000, mode="rwx"))
self.cpu.set_libxil({
"STDOUT_BASEADDRESS" : "0xE0000000",
"XPAR_PS7_DDR_0_S_AXI_BASEADDR" : "0x00100000",
"XPAR_PS7_DDR_0_S_AXI_HIGHADDR" : "0x1FFFFFFF",
})

# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

def finalize(self, *args, **kwargs):
super(BaseSoC, self).finalize(*args, **kwargs)
if self.cpu_type != "zynq7000":
return

libxil_path = os.path.join(self.builder.software_dir, 'libxil')
os.makedirs(os.path.realpath(libxil_path), exist_ok=True)
lib = os.path.join(libxil_path, 'embeddedsw')
if not os.path.exists(lib):
os.system("git clone --depth 1 https://github.com/Xilinx/embeddedsw {}".format(lib))

os.makedirs(os.path.realpath(self.builder.include_dir), exist_ok=True)
for header in [
'XilinxProcessorIPLib/drivers/uartps/src/xuartps_hw.h',
'lib/bsp/standalone/src/common/xil_types.h',
'lib/bsp/standalone/src/common/xil_assert.h',
'lib/bsp/standalone/src/common/xil_io.h',
'lib/bsp/standalone/src/common/xil_printf.h',
'lib/bsp/standalone/src/common/xstatus.h',
'lib/bsp/standalone/src/common/xdebug.h',
'lib/bsp/standalone/src/arm/cortexa9/xpseudo_asm.h',
'lib/bsp/standalone/src/arm/cortexa9/xreg_cortexa9.h',
'lib/bsp/standalone/src/arm/cortexa9/xil_cache.h',
'lib/bsp/standalone/src/arm/cortexa9/xparameters_ps.h',
'lib/bsp/standalone/src/arm/cortexa9/xil_errata.h',
'lib/bsp/standalone/src/arm/cortexa9/xtime_l.h',
'lib/bsp/standalone/src/arm/common/xil_exception.h',
'lib/bsp/standalone/src/arm/common/gcc/xpseudo_asm_gcc.h',
]:
shutil.copy(os.path.join(lib, header), self.builder.include_dir)
write_to_file(os.path.join(self.builder.include_dir, 'bspconfig.h'),
'#define FPU_HARD_FLOAT_ABI_ENABLED 1')
write_to_file(os.path.join(self.builder.include_dir, 'xparameters.h'), '''
#ifndef __XPARAMETERS_H
#define __XPARAMETERS_H

#include "xparameters_ps.h"

#define STDOUT_BASEADDRESS 0xE0000000
#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x1FFFFFFF

#endif
''')

# Build --------------------------------------------------------------------------------------------

def main():
Expand All @@ -177,10 +135,6 @@ def main():
**parser.soc_argdict
)
builder = Builder(soc, **parser.builder_argdict)
if args.cpu_type == "zynq7000":
soc.builder = builder
builder.add_software_package('libxil')
builder.add_software_library('libxil')
if args.build:
builder.build(**parser.toolchain_argdict)

Expand Down
58 changes: 6 additions & 52 deletions litex_boards/targets/digilent_zedboard.py
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Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -11,8 +11,6 @@
from litex.gen import *

from litex_boards.platforms import digilent_zedboard
from litex.build.tools import write_to_file


from litex.soc.cores.clock import *
from litex.soc.integration.soc import *
Expand Down Expand Up @@ -57,7 +55,7 @@ def __init__(self, toolchain="vivado", sys_clk_freq=100e6, with_led_chaser=True,
platform.add_extension(usb_pmod_io("pmodb"))
if kwargs.get("uart_name", "serial") == "serial": kwargs["uart_name"] = "usb_uart"
else:
kwargs["no_uart"] = True
kwargs["with_uart"] = False

# CRG --------------------------------------------------------------------------------------
use_ps7_clk = (kwargs.get("cpu_type", None) == "zynq7000")
Expand All @@ -84,58 +82,18 @@ def __init__(self, toolchain="vivado", sys_clk_freq=100e6, with_led_chaser=True,
linker = True)
)
self.constants["CONFIG_CLOCK_FREQUENCY"] = 666666687
self.cpu.set_libxil({
"STDOUT_BASEADDRESS" : "0xE0001000",
"XPAR_PS7_DDR_0_S_AXI_BASEADDR" : "0x00100000",
"XPAR_PS7_DDR_0_S_AXI_HIGHADDR" : "0x3FFFFFFF",
})

# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

def finalize(self, *args, **kwargs):
super(BaseSoC, self).finalize(*args, **kwargs)
if self.cpu_type != "zynq7000":
return

libxil_path = os.path.join(self.builder.software_dir, 'libxil')
os.makedirs(os.path.realpath(libxil_path), exist_ok=True)
lib = os.path.join(libxil_path, 'embeddedsw')
if not os.path.exists(lib):
os.system("git clone --depth 1 https://github.com/Xilinx/embeddedsw {}".format(lib))

os.makedirs(os.path.realpath(self.builder.include_dir), exist_ok=True)
for header in [
'XilinxProcessorIPLib/drivers/uartps/src/xuartps_hw.h',
'lib/bsp/standalone/src/common/xil_types.h',
'lib/bsp/standalone/src/common/xil_assert.h',
'lib/bsp/standalone/src/common/xil_io.h',
'lib/bsp/standalone/src/common/xil_printf.h',
'lib/bsp/standalone/src/common/xstatus.h',
'lib/bsp/standalone/src/common/xdebug.h',
'lib/bsp/standalone/src/arm/cortexa9/xpseudo_asm.h',
'lib/bsp/standalone/src/arm/cortexa9/xreg_cortexa9.h',
'lib/bsp/standalone/src/arm/cortexa9/xil_cache.h',
'lib/bsp/standalone/src/arm/cortexa9/xparameters_ps.h',
'lib/bsp/standalone/src/arm/cortexa9/xil_errata.h',
'lib/bsp/standalone/src/arm/cortexa9/xtime_l.h',
'lib/bsp/standalone/src/arm/common/xil_exception.h',
'lib/bsp/standalone/src/arm/common/gcc/xpseudo_asm_gcc.h',
]:
shutil.copy(os.path.join(lib, header), self.builder.include_dir)
write_to_file(os.path.join(self.builder.include_dir, 'bspconfig.h'),
'#define FPU_HARD_FLOAT_ABI_ENABLED 1')
write_to_file(os.path.join(self.builder.include_dir, 'xparameters.h'), '''
#ifndef __XPARAMETERS_H
#define __XPARAMETERS_H

#include "xparameters_ps.h"

#define STDOUT_BASEADDRESS 0xE0001000
#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x3FFFFFFF

#endif
''')

# Build --------------------------------------------------------------------------------------------

def main():
Expand All @@ -151,10 +109,6 @@ def main():
**parser.soc_argdict
)
builder = Builder(soc, **parser.builder_argdict)
if args.cpu_type == "zynq7000":
soc.builder = builder
builder.add_software_package('libxil')
builder.add_software_library('libxil')
if args.build:
builder.build(**parser.toolchain_argdict)

Expand Down
57 changes: 5 additions & 52 deletions litex_boards/targets/puzhi_p7_starlite.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -12,8 +12,6 @@

from litex_boards.platforms import puzhi_p7_starlite

from litex.build.tools import write_to_file

from litex.soc.integration.soc import *
from litex.soc.integration.soc import SoCRegion
from litex.soc.integration.builder import *
Expand Down Expand Up @@ -119,6 +117,11 @@ def __init__(self, variant="xc7z020", toolchain="vivado", sys_clk_freq=100e6,

# Enable SDIO.
self.cpu.add_sdio(0, "MIO 40 .. 45", None, None, None)
self.cpu.set_libxil({
"STDOUT_BASEADDRESS" : "0xE0000000",
"XPAR_PS7_DDR_0_S_AXI_BASEADDR" : "0x00100000",
"XPAR_PS7_DDR_0_S_AXI_HIGHADDR" : "0x1FFFFFFF",
})

if not with_ps7 and (with_ethernet or with_etherbone):
self.ethphy = LiteEthPHYRGMII(
Expand All @@ -135,51 +138,6 @@ def __init__(self, variant="xc7z020", toolchain="vivado", sys_clk_freq=100e6,
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

def finalize(self, *args, **kwargs):
super(BaseSoC, self).finalize(*args, **kwargs)
if self.cpu_type != "zynq7000":
return

libxil_path = os.path.join(self.builder.software_dir, 'libxil')
os.makedirs(os.path.realpath(libxil_path), exist_ok=True)
lib = os.path.join(libxil_path, 'embeddedsw')
if not os.path.exists(lib):
os.system("git clone --depth 1 https://github.com/Xilinx/embeddedsw {}".format(lib))

os.makedirs(os.path.realpath(self.builder.include_dir), exist_ok=True)
for header in [
'XilinxProcessorIPLib/drivers/uartps/src/xuartps_hw.h',
'lib/bsp/standalone/src/common/xil_types.h',
'lib/bsp/standalone/src/common/xil_assert.h',
'lib/bsp/standalone/src/common/xil_io.h',
'lib/bsp/standalone/src/common/xil_printf.h',
'lib/bsp/standalone/src/common/xstatus.h',
'lib/bsp/standalone/src/common/xdebug.h',
'lib/bsp/standalone/src/arm/cortexa9/xpseudo_asm.h',
'lib/bsp/standalone/src/arm/cortexa9/xreg_cortexa9.h',
'lib/bsp/standalone/src/arm/cortexa9/xil_cache.h',
'lib/bsp/standalone/src/arm/cortexa9/xparameters_ps.h',
'lib/bsp/standalone/src/arm/cortexa9/xil_errata.h',
'lib/bsp/standalone/src/arm/cortexa9/xtime_l.h',
'lib/bsp/standalone/src/arm/common/xil_exception.h',
'lib/bsp/standalone/src/arm/common/gcc/xpseudo_asm_gcc.h',
]:
shutil.copy(os.path.join(lib, header), self.builder.include_dir)
write_to_file(os.path.join(self.builder.include_dir, 'bspconfig.h'),
'#define FPU_HARD_FLOAT_ABI_ENABLED 1')
write_to_file(os.path.join(self.builder.include_dir, 'xparameters.h'), '''
#ifndef __XPARAMETERS_H
#define __XPARAMETERS_H

#include "xparameters_ps.h"

#define STDOUT_BASEADDRESS 0xE0000000
#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x1FFFFFFF

#endif
''')

# Build --------------------------------------------------------------------------------------------

def main():
Expand Down Expand Up @@ -213,11 +171,6 @@ def main():
)

builder = Builder(soc, **parser.builder_argdict)
if args.cpu_type == "zynq7000":
soc.builder = builder
builder.add_software_package('libxil')
builder.add_software_library('libxil')

if args.build:
builder.build(**parser.toolchain_argdict)

Expand Down
6 changes: 6 additions & 0 deletions litex_boards/targets/redpitaya.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -91,6 +91,12 @@ def __init__(self, board, sys_clk_freq=100e6, with_led_chaser=True, **kwargs):
# Enable Ethernet.
self.cpu.add_ethernet(0, "MIO 16 .. 27", "MIO 52 .. 53")

self.cpu.set_libxil({
"STDOUT_BASEADDRESS" : "XPS_UART0_BASEADDR",
"XPAR_PS7_DDR_0_S_AXI_BASEADDR" : "0x00100000",
"XPAR_PS7_DDR_0_S_AXI_HIGHADDR" : "0x1FFFFFFF",
})

# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.leds = LedChaser(
Expand Down
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