Add a test case

Author: uenoku

lib/Conversion/FIRRTLToHW/LowerToHW.cpp

@@ -1082,8 +1082,9 @@ void FIRRTLModuleLowering::emitInstanceChoiceIncludeFile(
   }
 
   // Create the emit.file operation at the top level
-  auto emitFile = emit::FileOp::create(builder, circuit.getLoc(),
-                                       includeFileName, circuitNamespace.newName(includeFileName));
+  auto emitFile =
+      emit::FileOp::create(builder, circuit.getLoc(), includeFileName,
+                           circuitNamespace.newName(includeFileName));
   OpBuilder::InsertionGuard g(builder);
   builder.setInsertionPointToStart(&emitFile.getBodyRegion().front());
 
@@ -1092,8 +1093,8 @@ void FIRRTLModuleLowering::emitInstanceChoiceIncludeFile(
     SmallString<256> headerComment;
     llvm::raw_svector_ostream os(headerComment);
     os << "// Specialization file for public module: "
-       << publicModuleName.getValue() << "\n";
-    os << "// Option: " << optionName.getValue()
+       << publicModuleName.getValue() << "\n"
+       << "// Option: " << optionName.getValue()
        << ", Case: " << caseName.getValue() << "\n";
     emit::VerbatimOp::create(builder, circuit.getLoc(),
                              builder.getStringAttr(headerComment));
@@ -1142,7 +1143,8 @@ void FIRRTLModuleLowering::emitInstanceChoiceIncludeFile(
 
   // Set output file attribute .svh files should be excluded from file list
   emitFile->setAttr("output_file", hw::OutputFileAttr::getFromFilename(
-      builder.getContext(), includeFileName, /*excludeFromFileList=*/true));
+                                       builder.getContext(), includeFileName,
+                                       /*excludeFromFileList=*/true));
 }
 
 /// Creates one include file per public module and option case following the

test/firtool/instance-choice.fir

@@ -0,0 +1,48 @@
+; RUN: firtool %s | FileCheck %s
+
+FIRRTL version 5.1.0
+circuit top:
+  option Platform:
+    FPGA
+
+  module DefaultTarget:
+    output result: UInt<32>
+
+    connect result, UInt<32>(0)
+
+  module FPGATarget:
+    output result: UInt<32>
+
+    connect result, UInt<32>(20)
+
+  public module top:
+    input clk: Clock
+    input rst: UInt<1>
+    ; CHECK:       wire [31:0] proc_result;
+    ; CHECK-NEXT:  `ifdef [[OPTION_NAME:.+]]
+    ; CHECK-NEXT:    FPGATarget proc_FPGA (
+    ; CHECK-NEXT:      .result (proc_result)
+    ; CHECK-NEXT:    );
+    ; CHECK-NEXT:  `else
+    ; CHECK-NEXT:    DefaultTarget proc_default (
+    ; CHECK-NEXT:      .result (proc_result)
+    ; CHECK-NEXT:    );
+    ; CHECK-NEXT:    `ifndef [[TARGET_NAME:.+]]
+    ; CHECK-NEXT:      `define [[TARGET_NAME]] proc_default
+    ; CHECK-NEXT:    `endif
+    ; CHECK-NEXT:  `endif
+    instchoice proc of DefaultTarget, Platform:
+      FPGA => FPGATarget
+
+    printf(clk, UInt<1>(1), "resul: %d\n", proc.result)
+; CHECK-LABEL: // ----- 8< ----- FILE "targets_top_Platform_FPGA.svh" ----- 8< -----
+; CHECK:       `ifndef [[OPTION_NAME]]
+; CHECK-NEXT:    `define [[OPTION_NAME]]
+; CHECK-NEXT:  `endif
+; CHECK-NEXT:  `ifdef [[TARGET_NAME]]
+; CHECK-NEXT:    `_ERROR_[[TARGET_NAME]]_must_not_be_set
+; CHECK-NEXT:  `else 
+; CHECK-NEXT:    `define [[TARGET_NAME]] proc_FPGA
+; CHECK-NEXT:  `endif
+
+