Skip to content

Pull requests: llvm/circt

New pull request New
249 Open 7,728 Closed
249 Open 7,728 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Reviews
Filter by reviews
No reviews Review required Approved review Changes requested
Assignee
Filter by who’s assigned
Assigned to nobody Loading
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Pull requests list

[CombToSynth] Add a lowering for mod/div where rhs is constant
#10584 opened Jun 4, 2026 by okekayode Contributor Loading…
[RTG][LinearScanRegisterAllocation] Add error message to avoid silent failures RTG Involving the `rtg` dialect
#10581 opened Jun 3, 2026 by maerhart Member Loading…
2
[Moore][ImportVerilog] Add %c format to FormatString pipeline
#10580 opened Jun 3, 2026 by VecoMr Contributor Loading…
3
[Debug] [1/14] Add EnumDefOp, SubFieldOp, and ModuleInfoOp to the Debug dialect
#10579 opened Jun 3, 2026 by fkhaidari Loading…
5
[ESI] Slim down manifest ESI
#10578 opened Jun 2, 2026 by teqdruid Contributor • Draft
5
[LTL][FIRRTL] Require non-negative LTL delay bounds
#10576 opened Jun 2, 2026 by Clo91eaf Contributor Loading…
1
[FIRRTL] Replace remove-unused-ports with port-only IMDCE mode
#10575 opened Jun 2, 2026 by uenoku Member Loading…
1
20
[HW] Change specification of union operations, NFC HW Involving the `hw` dialect
#10567 opened May 31, 2026 by fzi-hielscher Contributor Loading…
2
[LLHD] Fix incorrect mux generation in remove-control-flow
#10566 opened May 31, 2026 by vasyavasilevs Loading…
1
[Synth] Add declarative cut rewrite pattern and yield op
#10565 opened May 31, 2026 by okekayode Contributor Loading…
22
Add CIRCT standalone example
#10564 opened May 30, 2026 by uenoku Member Loading…
4
[ExportVerilog] Add a lowering option for always emitting begin/end
#10563 opened May 29, 2026 by uenoku Member Loading…
1
[Moore][ImportVerilog] Replace $sformat/$swrite string dispatch with ksn
#10557 opened May 28, 2026 by VecoMr Contributor Loading…
2
[Moore][Sim][SV] Add $strobe[boh] lowering via sim.defer
#10556 opened May 28, 2026 by VecoMr Contributor • Draft
3
[OM] Simplify evaluator placeholder handling, NFCI
#10555 opened May 28, 2026 by uenoku Member Loading…
1
[RFC][Sim] Add declarations and reads for externally controlled configuration bits
#10552 opened May 27, 2026 by nanjo712 Contributor Loading…
9
[Arc] Lower hw.triggered in Arc Arc Involving the `arc` dialect
#10550 opened May 27, 2026 by nanjo712 Contributor Loading…
2
[ImportVerilog] Add support for countones.
#10549 opened May 27, 2026 by jpienaar Member Loading…
9
[FIRRTLToHW] Add support for lower-to-core in firrtl.fflush
#10545 opened May 26, 2026 by nanjo712 Contributor Loading…
14
[LTL] Add ClockedAtomOp description
#10541 opened May 24, 2026 by Clo91eaf Contributor Loading…
5
[FIRRTLToHW] Remove the SYNTHESIS guard in printf/flush lowering path
#10526 opened May 22, 2026 by nanjo712 Contributor Loading…
30
[Synth] Add SAT-based exact synthesis pass
#10493 opened May 18, 2026 by uenoku Member Loading…
1
Bump slang 11.0
#10488 opened May 16, 2026 by mi-and-core • Draft
1
[HW] Add forceable wire support with HW RefType
#10447 opened May 12, 2026 by prithayan Contributor • Draft
[DRAFT][FIRRTLToHW] Emit sim.proc.print instead of sim.print
#10441 opened May 12, 2026 by nanjo712 Contributor • Draft
ProTip! Add no:assignee to see everything that’s not assigned.