[HWMemSimImpl] Avoid generation of 0 bit Value (#8393)

Ensure that 1 bit constant zero is generated instead of zero bit value from a comb.extract.
This fixes a bug when the memory data is 1 bit wide.

Author: prithayan

Diff for: lib/Dialect/Seq/Transforms/HWMemSimImpl.cpp

@@ -613,8 +613,13 @@ void HWMemSimImpl::generateMemory(HWModuleOp op, FirMemory mem) {
                     "j", [&](BlockArgument innerIndVar) {
                       auto rhs = b.create<sv::MacroRefExprSEOp>(
                           b.getIntegerType(randomWidth), "RANDOM");
-                      auto truncInnerIndVar = b.createOrFold<comb::ExtractOp>(
-                          innerIndVar, 0, llvm::Log2_64_Ceil(mem.dataWidth));
+                      Value truncInnerIndVar;
+                      if (mem.dataWidth <= 1)
+                        truncInnerIndVar =
+                            b.create<hw::ConstantOp>(b.getI1Type(), 0);
+                      else
+                        truncInnerIndVar = b.createOrFold<comb::ExtractOp>(
+                            innerIndVar, 0, llvm::Log2_64_Ceil(mem.dataWidth));
                       auto lhs = b.create<sv::IndexedPartSelectInOutOp>(
                           randomMemReg, truncInnerIndVar, randomWidth, false);
                       b.create<sv::BPAssignOp>(lhs, rhs);

Diff for: test/Dialect/Seq/hw-memsim.mlir

@@ -472,3 +472,39 @@ hw.module.generated @TestFragment, @FIRRTLMem(
 
 // CHECK-LABEL: hw.module private @TestFragment
 // CHECK-SAME:    emit.fragments = [@Fragment]
+
+// Test an i1 memory.
+ hw.module.generated @ram_2x1, @FIRRTLMem(
+  in %R0_addr : i1,
+  in %R0_en : i1,
+  in %R0_clk : i1,
+  out R0_data : i1,
+  in %W0_addr : i1,
+  in %W0_en : i1,
+  in %W0_clk : i1,
+  in %W0_data : i1
+  ) attributes {
+  depth = 2 : i64,
+  initFilename = "",
+  initIsBinary = false,
+  initIsInline = false,
+  maskGran = 1 : ui32,
+  numReadPorts = 1 : ui32,
+  numReadWritePorts = 0 : ui32,
+  numWritePorts = 1 : ui32,
+  readLatency = 0 : ui32,
+  readUnderWrite = 0 : i32,
+  width = 1 : ui32,
+  writeClockIDs = [0 : i32],
+  writeLatency = 1 : ui32,
+  writeUnderWrite = 1 : i32}
+
+// CHECK-LABEL: hw.module private @ram_2x1
+// CHECK:        %[[c0_i6:.+]] = hw.constant 0 : i6
+// CHECK-NEXT:   %[[c_32_i6:.+]] = hw.constant -32 : i6
+// CHECK-NEXT:   %[[c_32_i6_0:.+]] = hw.constant -32 : i6
+// CHECK-NEXT:   sv.for %[[J:.+]] = %[[c0_i6]] to %[[c_32_i6]] step %[[c_32_i6_0]] : i6 {
+// CHECK-NEXT:     %[[RANDOM:.+]] = sv.macro.ref.expr.se @RANDOM() : () -> i32
+// CHECK-NEXT:     %false = hw.constant false
+// CHECK-NEXT:     %[[V7:.+]] = sv.indexed_part_select_inout %_RANDOM_MEM[%false : 32] : !hw.inout<i32>, i1
+// CHECK-NEXT:     sv.bpassign %[[V7]], %RANDOM : i32