Skip to content

Commit 3f82acb

Browse files
authored
Bump LLVM to 4d5a963eaf6ad209487a321dee7f0cd2a0f98477. (#8336)
After llvm/llvm-project@f3e5594, DRR patterns will now generate calls to builders that use Properties, for dialects that use Properties. Since we skip default builders for RegOp, we need a builder that accepts Properties, since the DRR patterns assume such a builder exists.
1 parent 8c1a8f1 commit 3f82acb

File tree

2 files changed

+9
-1
lines changed

2 files changed

+9
-1
lines changed

include/circt/Dialect/FIRRTL/FIRRTLDeclarations.td

+8
Original file line numberDiff line numberDiff line change
@@ -407,6 +407,14 @@ def RegOp : HardwareDeclOp<"reg", [Forceable, DeclareOpInterfaceMethods<CombData
407407
assert(resultTypes.size() >= 1u && "mismatched number of return types");
408408
odsState.addTypes(resultTypes);
409409
}]>,
410+
OpBuilder<(ins "::mlir::TypeRange":$resultTypes, "::mlir::ValueRange":$operands,
411+
CArg<"const Properties &","{}">:$properties), [{
412+
assert(operands.size() == 1u && "mismatched number of parameters");
413+
odsState.addOperands(operands);
414+
odsState.useProperties(const_cast<Properties &>(properties));
415+
assert(resultTypes.size() >= 1u && "mismatched number of return types");
416+
odsState.addTypes(resultTypes);
417+
}]>,
410418
OpBuilder<(ins "::mlir::Type":$elementType,
411419
"::mlir::Value":$clockVal,
412420
"::mlir::StringAttr":$name,

llvm

Submodule llvm updated 6224 files

0 commit comments

Comments
 (0)