[ImportVerilog] Introduce the semantic analysis of slang

Initially, the intention was to check the validity of variable assignments. But in the end, introduce the semantic analysis of slang. However,  only add test cases for variable assignments--it is illegal to assign to a variable with multiple continuous assignments or mix continuous and procedural assignments.

Author: sunhailong2001

lib/Conversion/ImportVerilog/AssertionExpr.cpp

@@ -426,9 +426,11 @@ Value Context::convertAssertionCallExpression(
     value = this->convertRvalueExpression(*args[0]);
     originalType = value.getType();
     valTy = dyn_cast<moore::IntType>(value.getType());
+
+    // The semantic analysis of slang will handle this error, so extra error
+    // emission here is not necessary, but we need to check for it to avoid
+    // crashes in case of malformed input.
     if (!valTy) {
-      mlir::emitError(loc) << "expected integer argument for system call `"
-                           << subroutine.name << "`";
       return {};
     }
     // If the value is four-valued, we need to map it to two-valued before we

lib/Conversion/ImportVerilog/ImportVerilog.cpp

@@ -26,6 +26,7 @@
 #include "llvm/ADT/Hashing.h"
 #include "llvm/Support/SourceMgr.h"
 
+#include "slang/analysis/AnalysisManager.h"
 #include "slang/diagnostics/DiagnosticClient.h"
 #include "slang/driver/Driver.h"
 #include "slang/parsing/Preprocessor.h"
@@ -274,6 +275,11 @@ LogicalResult ImportDriver::importVerilog(ModuleOp module) {
   // Elaborate the input.
   auto compileTimer = ts.nest("Verilog elaboration");
   auto compilation = driver.createCompilation();
+
+  // Semantic analysis
+  auto analysisTimer = ts.nest("Semantic analysis");
+  driver.runAnalysis(*compilation);
+
   for (auto &diag : compilation->getAllDiagnostics())
     driver.diagEngine.issue(diag);
   if (!parseSuccess || driver.diagEngine.getNumErrors() > 0)

test/Conversion/ImportVerilog/errors.sv

@@ -180,7 +180,7 @@ endfunction
 // -----
 module Foo;
   string b;
-  // expected-error @below {{expected integer argument for system call `$past`}}
+  // expected-error @below {{sequence has no explicit clocking event and one cannot be inferred from context}}
   assert property ($past(b));
 endmodule
 
@@ -200,3 +200,52 @@ module Foo;
     s[0] = b;
   end
 endmodule
+
+// -----
+module Foo;
+	int v = 1;
+
+  // expected-error @+2 {{cannot mix continuous and procedural assignments to variable 'v'}}
+  // expected-remark @-3 {{also assigned here}}
+	assign v = 12;
+endmodule
+
+// -----
+module Foo;
+	int v;
+
+  // expected-error @+3 {{cannot have multiple continuous assignments to variable 'v'}}
+  // expected-remark @below {{also assigned here}}
+	assign v = 12;
+	assign v = 13;
+endmodule
+
+// -----
+module Foo;
+	wire clk = 0;
+	int v;
+
+  // expected-error @+3 {{cannot mix continuous and procedural assignments to variable 'v'}}
+  // expected-remark @below {{also assigned here}}
+	assign v = 12;
+	always @(posedge clk) v <= ~v;
+endmodule
+
+// -----
+module Foo;
+	wire clk = 0;
+	int v;
+
+  // expected-error @+3 {{cannot mix continuous and procedural assignments to variable 'v'}}
+  // expected-remark @below {{also assigned here}}
+	always @(posedge clk) v <= ~v;
+	assign v = 12;
+endmodule
+
+// -----
+module Foo;
+  logic a;
+
+  // expected-error @below {{'always' procedure does not advance time and so will create a simulation deadlock}}
+  always a = ~a;
+endmodule

test/Conversion/ImportVerilog/procedures.sv

@@ -19,12 +19,6 @@ module Foo;
   // CHECK-NEXT: }
   final foo();
 
-  // CHECK:      moore.procedure always {
-  // CHECK-NEXT:   func.call @foo
-  // CHECK-NEXT:   moore.return
-  // CHECK-NEXT: }
-  always foo();
-
   // CHECK:      moore.procedure always_comb {
   // CHECK-NEXT:   func.call @foo
   // CHECK-NEXT:   moore.return