@@ -38,3 +38,39 @@ module {
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return %2 : i32
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}
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}
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+
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+ // -----
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+
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+ // Test multiple return values.
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+
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+ // CHECK: module {
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+ // CHECK-NEXT: calyx.program "main" {
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+ // CHECK-NEXT: calyx.component @main(%in0: i32, %in1: i32, %clk: i1 {clk}, %reset: i1 {reset}, %go: i1 {go}) -> (%out0: i32, %out1: i32, %done: i1 {done}) {
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+ // CHECK-NEXT: %true = hw.constant true
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+ // CHECK-NEXT: %ret_arg1_reg.in, %ret_arg1_reg.write_en, %ret_arg1_reg.clk, %ret_arg1_reg.reset, %ret_arg1_reg.out, %ret_arg1_reg.done = calyx.register "ret_arg1_reg" : i32, i1, i1, i1, i32, i1
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+ // CHECK-NEXT: %ret_arg0_reg.in, %ret_arg0_reg.write_en, %ret_arg0_reg.clk, %ret_arg0_reg.reset, %ret_arg0_reg.out, %ret_arg0_reg.done = calyx.register "ret_arg0_reg" : i32, i1, i1, i1, i32, i1
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+ // CHECK-NEXT: calyx.wires {
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+ // CHECK-NEXT: calyx.assign %out1 = %ret_arg1_reg.out : i32
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+ // CHECK-NEXT: calyx.assign %out0 = %ret_arg0_reg.out : i32
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+ // CHECK-NEXT: calyx.group @ret_assign_0 {
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+ // CHECK-NEXT: calyx.assign %ret_arg0_reg.in = %in0 : i32
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+ // CHECK-NEXT: calyx.assign %ret_arg0_reg.write_en = %true : i1
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+ // CHECK-NEXT: calyx.assign %ret_arg1_reg.in = %in1 : i32
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+ // CHECK-NEXT: calyx.assign %ret_arg1_reg.write_en = %true : i1
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+ // CHECK-NEXT: %0 = comb.and %ret_arg0_reg.done, %ret_arg1_reg.done : i1
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+ // CHECK-NEXT: calyx.group_done %true, %0 ? : i1
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+ // CHECK-NEXT: }
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+ // CHECK-NEXT: }
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+ // CHECK-NEXT: calyx.control {
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+ // CHECK-NEXT: calyx.seq {
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+ // CHECK-NEXT: calyx.enable @ret_assign_0
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+ // CHECK-NEXT: }
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+ // CHECK-NEXT: }
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+ // CHECK-NEXT: }
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+ // CHECK-NEXT: }
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+ // CHECK-NEXT: }
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+ module {
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+ func @main (%a0 : i32 , %a1 : i32 ) -> (i32 , i32 ) {
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+ return %a0 , %a1 : i32 , i32
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+ }
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+ }
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