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Using SystemVerilog Interfaces in Other Interfaces #1171

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@seldridge

Description

I've got a situation where I'd like to have one SystemVerilog interface instantiate another. I'd like to start a discussion about how we can represent nested interfaces in the IR (as this doesn't currently seem to work).

As an example, I need to represent the following (taken from #1170):

interface sub_regBundle;
  logic [15:0] b;
  logic [15:0] a;
endinterface

interface View;
  sub_regBundle sub_regBundle();
endinterface

With the current structure of sv::InterfaceOp there are a number of problems:

  1. Each sv::InterfaceOp is both a symbol and has a symbol table. This complicates things where you need to define an interface member which needs to resolve a symbol outside of its scope. This should be able to resolve any public symbol and may motivate removing the symbol table from an InterfaceOp. (Why is there a symbol table on the InterfaceOp?)
  2. There's a bunch of missing logic related to handling this. Currently, this doesn't seem to verify correctly as interfaces aren't handled in hw::getBitWidth.

To work around all this, I'm resorting to using sv::VerbatimOp in #1170.

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