[ExportVerilog] Add support for bit swapping idiom

[lattner]

ExportVerilog emits a concat that bitswaps like this:

thing = {io_in1[0], io_in1[1], io_in1[2], io_in1[3], io_in1[4]...}

but there are better idioms for this. We could generate them directly, and we may want to introduce a comb op for bitswapping.