[LowerToHW] Use type decl for Bundle type lowering

[uenoku]

If there are large structs in ports, we might get long lines. For example(from FPU.fir),

; circt-opt %s -export-verilog
hw.module @Long(%clock: i1, %io_cp_req_bits: !hw.struct<cmd: i5, ldst: i1, wen: i1, ren1: i1, ren2: i1, ren3: i1, 
                               swap12: i1, swap23: i1, single: i1, fromint: i1, toint: i1, fastpipe: i1, fma: i1, div: i1, sqrt: i1, 
                               wflags: i1, rm: i3, typ: i2, in1: i65, in2: i65, in3: i65>)  {
}

will generate

module Long(     // foo.mlir:1:1
  input                                                                                                                                                                                                                                                                                                                           clock,
  input struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } io_cp_req_bits);

endmodule

This looks not good so we may consider to use type decl at module scope.