[ExportVerilog] Remove temporary for aggregate outputs

[uenoku]

For the following fir,

 module Bar:
    input a: {clock: Clock, reset: UInt<1>},
    output b: {clock: Clock, reset: UInt<1>}
    b <= a

In aggregate preservation mode, we currently emit this:

module Bar(	// foo.fir:2:10
  input  struct packed {logic clock; logic reset; } a,
  output struct packed {logic clock; logic reset; } b);

  wire struct packed {logic clock; logic reset; } _b_output;

  assign _b_output.clock = a.clock;
  assign _b_output.reset = a.reset;
  assign b = _b_output;	// foo.fir:2:10
endmodule

It is better not to emit temporary _b_output, like:

module Bar(	// foo.fir:2:10
  input  struct packed {logic clock; logic reset; } a,
  output struct packed {logic clock; logic reset; } b);

  assign b.clock = a.clock;	// foo.fir:5:7
  assign b.reset = a.reset;	// foo.fir:5:7
endmodule