[ExportVerilog] Consider to cache results of `isExpressionUnableToInline`

[uenoku]

isExpressionUnableToInline(op) checks all users to determine the given operation is allowed to emit inline.
I haven't done proper profiling but it might be possible to speed up ExportVerilog by cacheing the result of isExpressionUnableToInline.

[lattner]

Yeah this is a significant amount of compile time. Instead of caching, is there a better algorithm to use here that isnt' quadratic?

[uenoku]

Yeah this is a significant amount of compile time. Instead of caching, is there a better algorithm to use here that isnt' quadratic?

I agree. Currently, we are looking at users from operation, but we can make the direction opposite;
walk every operation and mark operands if the operation violates inlinng rule. The logic might become more complicated though.