[ExportVerilog] Incorrect verilog output for bitcast + zero width aggregate types

[uenoku]

We are emitting zero bit width array/struct as one bit element. This is problem when we use bitcast for them.

hw.module @top(%source: i1) -> (b: !hw.struct<zero: !hw.array<1xi0>, c: i1>) {
    %cast = hw.bitcast %source: (i1) -> !hw.struct<zero: !hw.array<1xi0>, c: i1>
    hw.output %cast : !hw.struct<zero: !hw.array<1xi0>, c: i1>
 }

module top(	// out.mlir:2:3
  input                                                            source,
  output struct packed {logic [0:0]/*Zero Width*/ zero; logic c; } b);
 
  assign b = source;	// out.mlir:3:12, :4:5
endmodule