[ExportVerilog] Omit bitwidth of constant array index

```mlir
hw.module @Foo(%a: !hw.array<1xi1>) -> (b: i1) {
  %false = hw.constant false
  %0 = hw.array_get %a[%false] : !hw.array<1xi1>
  hw.output %0 : i1
}
```

```sv
module Foo(	// foo.fir:2:10
  input  [0:0] a,
  output       b);

  assign b = a[1'h0];	// foo.fir:2:10, :5:12
endmodule
```

I'm not 100% sure it is always legal but can't we just emit `assign b = a[0]` ?
