[PyCDE/CAPI] iverilog chokes on automatic logic

[mortbopet]

automatic logic can be circumvented by passing --lowering-options=disallowLocalVariables during --export-verilog.

For PyCDE, We'd want to be able to - at some point in the stack - to specify this variable. One point could be as a flag at the CAPI level:

circt/lib/Bindings/Python/CIRCTModule.cpp

Lines 86 to 90 in bc4c687

	m.def("export_verilog", [](MlirModule mod, py::object fileObject) {
	circt::python::PyFileAccumulator accum(fileObject, false);
	py::gil_scoped_release();
	mlirExportVerilog(mod, accum.getCallback(), accum.getUserData());
	});

As long as it is something which we can set when emitting RTL for @cocotestbench PyCDE runs.