Open
Description
This is a tracking issue for the reimplementation of HandshakeToFIRRTL to a HW/ESI-based implementation:
- Operators
- Mux
- Conditional branch
- Instance
- Buffer
- Seq
- Fifo: A fifo is most easily implemented when some memory abstraction can be targeted (ready/write pointers, transparency, ...). We currently have
seq.hlmem
but it would be nice to also have aseq.fifo
operation (which could lower to a seq.hlmem implementation).
- Constant
- Fork
- Join
- LazyFork
- Load
- Store
- Memory
- Ideally should lower to a
seq.hlmem
operation, see [Seq]seq.hlmem
ODS and rationale #3973
- Ideally should lower to a
- External memory
- Select
- Sync
- Pack
- Partially done - lowerings exist but semi-blocked by [ExportVerilog] Struct assignment patterns not supported for all tools #4043
- Unpack
- Support pruning
i0
logic- HandshakeToHW attempts to to keep special-case logic for handling
none
(soon to bei0
)-typed values. This implies that any handshake SSA value which isi0
still carries ready/valid/data semantics, however the data part of the bundle is of zero width. Given this style of lowering, we need a pass that is able to prune thei0
logic post-conversion (or keep it around until emission and let the emitter decide what to do with it).
- HandshakeToHW attempts to to keep special-case logic for handling
- Figure out how to support memories
- This will be ESI based, and should use an ESI service.
- Move integration tests from FIRRTL to HW implementation
- Remove HandshakeToFIRRTL