[ExportVerilog] "$name is not allowed in Verilog output" error does not fail pass

[dtzSiFive]

Encountered crafting test over here: #4589 (comment) .

Is currently reachable + executed as part of the verilog-errors.mlir test case:

hw.module.extern @parameter ()

=>

verilog-error.mlir:4:1: error: name "parameter" is not allowed in Verilog output
hw.module.extern @parameter ()
^
verilog-error.mlir:4:1: note: see current operation: 
"hw.module.extern"() ({
}) {argLocs = [], argNames = [], comment = "", function_type = () -> (), parameters = [], resultLocs = [], resultNames = [], sym_name = "parameter"} : () -> ()
// Generated by CIRCT 1.34.0g20230304_3ddf879
// external module parameter

As an aside, getting our error tests to check that pass/execution is not successful would be great, cc #4553 .