[ExportVerilog][SV] sv.interface instance name not Verilog-keyword mangled

[seldridge]

The instance name of an SV interface op is not mangled if it collides with a Verilog keyword when it should be.

Consider:

module {
  sv.interface @wire {}
  hw.module private @Foo() {
    %module = sv.interface.instance : !sv.interface<@wire>
    hw.output
  }
}

This is being output as the following when using circt-opt -export-verilog Foo.mlir:

// Generated by CIRCT unknown git version
interface module_0;
endinterface

module Foo();	// Foo.mlir:3:3
  wire_0 module();	// Foo.mlir:4:15
endmodule