[LegalizeNames] Typedecls need to be checked if they collide with reserved words

[youngar]

Running this example through circt-opt -export-verilog

hw.type_scope @scope {
  hw.typedecl @enum : !hw.enum<A, B, C>
}

gives

`ifndef _TYPESCOPE_scope
`define _TYPESCOPE_scope
  typedef enum bit [1:0] {enum_A, enum_B, enum_C} enum;
`endif // _TYPESCOPE_scope

vcs says:

Error-[SE] Syntax error
  Following verilog source has syntax error :
  "design.sv", 2: token is 'enum'
  typedef enum bit [1:0] {enum_A, enum_B, enum_C} enum
                                                      ^
  SystemVerilog  keyword 'enum' is not expected to be used in this context.