[ExportVerilog] `disallowPackedStructAssignments` also needs to consider `hw.aggregate_constant`

[mortbopet]

Currently, the following:

%16 = hw.aggregate_constant [0 : i32, 0 : i32, 0 : i32] : !hw.struct<field0: i32, field1: i32, field2: i32>

emits as

wire struct packed {logic [31:0] field0; logic [31:0] field1; logic [31:0] field2; }
    _GEN_1 = '{field0: 32'h0, field1: 32'h0, field2: 32'h0};

that is, emits a packed struct assignment, which should be disallowed when setting the disallowPackedStructAssignments flag.