How to remove _GEN wires?

[flexiot]

Here is a mux example. firtool generates some GEN wires as there are multiple callings.

But I would like to inline those GEN wires into the mux line just like the following code.

I tried to enable --disable-opt option. This option indeed can put GEN wires into the mux line, but this --disable-opt also can disable other optimization which is not expected.

Is it possible to just disable this small(not liked) optimization and keep other optimization?

[uenoku]

Is it possible to just disable this small(not liked) optimization and keep other optimization?

Currently there is no such an option. Multiply used expressions are spilled into temporary wires unless expressions are very simple (e.g. not, extract). I think it might make sense to create a lowering option to inline multiply used expressions but not sure the cost model and how much practically useful it is. I guess output sizes will easily grow exponentially. Just curios, why do you want to inline GEN for this case? Is there any tool that produces worse results?

[flexiot]

Is it possible to just disable this small(not liked) optimization and keep other optimization?

Currently there is no such an option. Multiply used expressions are spilled into temporary wires unless expressions are very simple (e.g. not, extract). I think it might make sense to create a lowering option to inline multiply used expressions but not sure the cost model and how much practically useful it is. I guess output sizes will easily grow exponentially. Just curios, why do you want to inline GEN for this case? Is there any tool that produces worse results?

Thanks for your reply. The reason to inline GEN is to make the generated system verilog more readable and more consistent with the chisel code as those GEN variables do not exist in the chisel code.