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Description
Verifier checks that else region is non-empty if present.
Current patterns can fail this verification, for example when the else region contains some control op that removes itself (emptyControl<OpTy>) the containing block is now newly empty and fails verification.
Caught by -DMLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS=ON..
cc #7047.
This can be observed with the following example from test/Dialect/Calyx/canonicalization.mlir:
module attributes {calyx.entrypoint = "main"} {
calyx.component @main(%go: i1 {go}, %clk: i1 {clk}, %reset: i1 {reset}) -> (%done: i1 {done}) {
%r.in, %r.write_en, %r.clk, %r.reset, %r.out, %r.done = calyx.register @r : i1, i1, i1, i1, i1, i1
%eq.left, %eq.right, %eq.out = calyx.std_eq @eq : i1, i1, i1
%c1_1 = hw.constant 1 : i1
calyx.wires {
calyx.comb_group @Cond {
calyx.assign %eq.left = %c1_1 : i1
calyx.assign %eq.right = %c1_1 : i1
}
calyx.group @A {
calyx.assign %r.in = %c1_1 : i1
calyx.assign %r.write_en = %c1_1 : i1
calyx.group_done %r.done : i1
}
}
calyx.control {
calyx.seq {
calyx.if %eq.out with @Cond {
calyx.seq {
calyx.enable @A
}
} else {
calyx.seq {
calyx.enable @A
}
}
}
}
}
}